Functional test of small-delay faults using SAT and Craig interpolation

2012 ◽  
Author(s):  
Matthias Sauer ◽  
Stefan Kupferschmid ◽  
Alexander Czutro ◽  
Ilia Polian ◽  
Sudhakar Reddy ◽  
...  
Keyword(s):  
Functional Test ◽  
Delay Faults ◽  
Craig Interpolation ◽  
Small Delay

Divide and Compact — Stochastic Space Compaction for Faster-than-at-Speed Test

2019 ◽  
Vol 28 (supp01) ◽  
pp. 1940001
Author(s):  
Alexander Sprenger ◽  
Sybille Hellebrand
Keyword(s):  
State Of The Art ◽  
Set Partitioning ◽  
Delay Faults ◽  
Clock Frequency ◽  
Speed Test ◽  
Proper Mapping ◽  
Small Delay ◽  
Stochastic Space ◽  
Partitioning Problem ◽  
Scan Chain

With shrinking feature sizes detecting small delay faults is getting more and more important. But not all small delay faults are detectable during at-speed test. By overclocking the circuit with several different test frequencies faster-than-at-speed test (FAST) is able to detect these hidden delay faults. If the clock frequency is increased, some outputs of the circuit may not have stabilized yet, and these outputs have to be considered as unknown ([Formula: see text]-values). These [Formula: see text]-values impede the test response compaction. In addition, the number and distribution of the [Formula: see text]-values vary with the clock frequency, and thus a very flexible [Formula: see text]-handling is needed for FAST. Most of the state-of-the-art solutions are not designed for these varying [Formula: see text]-profiles. Yet, the stochastic compactor by Mitra et al. can be adjusted to changing environments. It is easily programmable because it is controlled by weighted pseudo-random signals. But an optimal setup cannot be guaranteed in a FAST scenario. By partitioning the compactor into several smaller ones and a proper mapping of the scan outputs to the compactor inputs, the compactor can be better adapted to the varying [Formula: see text]-profiles. Finding the best setup can be formulated as a set partitioning problem. To solve this problem, several algorithms are presented. Experimental results show that independent from the scan chain configuration, the number of [Formula: see text]-values can be reduced significantly while the fault efficiency can be maintained. Additionally, it is shown that [Formula: see text]-reduction and fault efficiency can be adapted to user-defined goals.

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects

2008 ◽  
Author(s):  
Alejandro Czutro ◽  
Nicolas Houarche ◽  
Piet Engelke ◽  
Ilia Polian ◽  
Mariane Comte ◽  
...  
Keyword(s):  
Delay Faults ◽  
Small Delay ◽  
Open Defects ◽  
Resistive Open Defects

Circuit and Methodology for Testing Small Delay Faults in the Clock Network

2018 ◽  
Vol 37 (10) ◽  
pp. 2087-2097 ◽  
Author(s):  
Shao-Fu Yang ◽  
Zhi-Yuan Wen ◽  
Shi-Yu Huang ◽  
Kun-Han Tsai ◽  
Wu-Tung Cheng
Keyword(s):  
Delay Faults ◽  
Clock Network ◽  
Small Delay

A GPU-Based Fault Simulator for Small-Delay Faults

2013 ◽  
Vol 753-755 ◽  
pp. 2235-2242
Author(s):  
Ming Ming Peng ◽  
Ji Shun Kuang
Keyword(s):  
Integrated Circuit ◽  
Graphics Processing Unit ◽  
Fault Simulation ◽  
Processing Unit ◽  
Delay Faults ◽  
Clock Frequency ◽  
Simulation Engine ◽  
Small Delay ◽  
On Chip ◽  
Graphics Processing

In this paper, we explore the implementation of fault simulator for small-delay faults on Graphics Processing Unit (GPU). Nowadays the size of integrated circuit is getting smaller and smaller, the clock frequency has become faster and faster, which leads to the effects of small delay fault on chip and is also increasingly obvious. Small delay simulation has become highly important, it is directly related to the accuracy of product and its time to market. At the same time, small delay simulation is a very time consuming process, which requires constantly looking for ways to accelerate the simulation. In recent years, GPU has been used to accelerate the programs of intensive computation in many areas and has achieved very good results. Based on these two points, we consider combining the parallelism of small delay simulation with the high parallel computing ability of GPU to accelerate small delay simulation. Experimental results indicate that our approach is on average 42 when compared to the traditional fault simulation engine.

Sign in / Sign up

Export Citation Format

Share Document