Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling

2006 IEEE International Test Conference ◽

10.1109/test.2006.297693 ◽

2006 ◽

Cited By ~ 11

Author(s):

Soheil Samii ◽

Erik Larsson ◽

Krishnendu Chakrabarty ◽

Zebo Peng

Keyword(s):

Test Scheduling ◽

Power Modeling ◽

Test Power ◽

Soc Test

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Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2008.917974 ◽

2008 ◽

Vol 27 (5) ◽

pp. 973-977 ◽

Cited By ~ 21

Author(s):

S. Samii ◽

M. Selkala ◽

E. Larsson ◽

K. Chakrabarty ◽

Zebo Peng

Keyword(s):

Architecture Design ◽

Power Modeling ◽

Test Power ◽

Soc Test ◽

Test Architecture

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SOC test scheduling using simulated annealing

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197670 ◽

2003 ◽

Cited By ~ 36

Author(s):

Wei Zou ◽

S.M. Reddy ◽

I. Pomeranz ◽

Yu Huang

Keyword(s):

Simulated Annealing ◽

Test Scheduling ◽

Soc Test

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Static pin mapping and SOC test scheduling for cores with multiple test sets

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. ◽

10.1109/isqed.2003.1194716 ◽

2004 ◽

Cited By ~ 13

Author(s):

Yu Huang ◽

Wu-Tung Cheng ◽

Chien-Chung Tsai ◽

N. Mukherjee ◽

S.M. Reddy

Keyword(s):

Test Scheduling ◽

Multiple Test ◽

Soc Test ◽

Test Sets

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Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies

2009 Asian Test Symposium ◽

10.1109/ats.2009.15 ◽

2009 ◽

Cited By ~ 17

Author(s):

Chunhua Yao ◽

Kewal K. Saluja ◽

Parameswaran Ramanathan

Keyword(s):

Deep Submicron ◽

Test Scheduling ◽

Power Constraints ◽

Soc Test

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Core-based SoC test scheduling using evolutionary algorithm

The 2003 Congress on Evolutionary Computation, 2003. CEC '03. ◽

10.1109/cec.2003.1299880 ◽

2004 ◽

Author(s):

Yu Xia ◽

M. Chrzanowska-Jeske ◽

Benyi Wang

Keyword(s):

Evolutionary Algorithm ◽

Test Scheduling ◽

Soc Test

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NoC-Based SoC Test Scheduling Using Ant Colony Optimization

ETRI Journal ◽

10.4218/etrij.08.0107.0090 ◽

2008 ◽

Vol 30 (1) ◽

pp. 129-140 ◽

Cited By ~ 6

Author(s):

Jin-Ho Ahn ◽

Sungho Kang

Keyword(s):

Ant Colony Optimization ◽

Ant Colony ◽

Test Scheduling ◽

Soc Test

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An Improved SoC Test Scheduling Method Based on Simulated Annealing Algorithm

Journal of Physics Conference Series ◽

10.1088/1742-6596/806/1/012011 ◽

2017 ◽

Vol 806 ◽

pp. 012011

Author(s):

Jingjing Zheng ◽

Zhihang Shen ◽

Huaien Gao ◽

Bianna Chen ◽

Weida Zheng ◽

...

Keyword(s):

Simulated Annealing ◽

Simulated Annealing Algorithm ◽

Test Scheduling ◽

Soc Test ◽

Scheduling Method ◽

Annealing Algorithm

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Defect-aware SOC test scheduling

22nd IEEE VLSI Test Symposium, 2004. Proceedings. ◽

10.1109/vtest.2004.1299265 ◽

2004 ◽

Cited By ~ 25

Author(s):

E. Larsson ◽

J. Pouget ◽

Zebo Peng

Keyword(s):

Test Scheduling ◽

Soc Test

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Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation

2010 19th IEEE Asian Test Symposium ◽

10.1109/ats.2010.74 ◽

2010 ◽

Cited By ~ 10

Author(s):

Nima Aghaee ◽

Zhiyuan He ◽

Zebo Peng ◽

Petru Eles

Keyword(s):

Process Variation ◽

Test Scheduling ◽

Soc Test

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Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.244141 ◽

2006 ◽

Cited By ~ 1

Author(s):

Zhiyuan He ◽

Zebo Peng ◽

P. Eles

Keyword(s):

Set Partitioning ◽

Test Scheduling ◽

Test Set ◽

Soc Test ◽

Defect Probability

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