Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies

Author(s):  
Chunhua Yao ◽  
Kewal K. Saluja ◽  
Parameswaran Ramanathan
Author(s):  
HAIDAR M. HARMANANI ◽  
HASSAN A. SALAMY

This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.


2004 ◽  
Vol 20 (1) ◽  
pp. 61-78 ◽  
Author(s):  
Valentin Mureşan ◽  
Xiaojun Wang ◽  
Valentina Mureşan ◽  
Mircea Vlăduţiu

ETRI Journal ◽  
2008 ◽  
Vol 30 (1) ◽  
pp. 129-140 ◽  
Author(s):  
Jin-Ho Ahn ◽  
Sungho Kang

2017 ◽  
Vol 806 ◽  
pp. 012011
Author(s):  
Jingjing Zheng ◽  
Zhihang Shen ◽  
Huaien Gao ◽  
Bianna Chen ◽  
Weida Zheng ◽  
...  

2013 ◽  
Vol 26 (7) ◽  
pp. 591-596
Author(s):  
Wei Wang ◽  
Zhuowei Lin ◽  
Tian Chen ◽  
Jun Liu ◽  
Fang Fang ◽  
...  

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