Switching Mechanisms Triggered by a Collector Voltage Ramp in Avalanche Transistors With Short-Connected Base and Emitter

2016 ◽  
Vol 63 (8) ◽  
pp. 3044-3048 ◽  
Author(s):  
Sergey N. Vainshtein ◽  
Guoyong Duan ◽  
Alexey V. Filimonov ◽  
Juha T. Kostamovaara
Keyword(s):  
Collector Voltage ◽  
Voltage Ramp

Assessment of Reliability of cap layers used in Cu-Black DiamondTM Interconnects

2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong
Keyword(s):  
Dielectric Layer ◽  
Dielectric Breakdown ◽  
Copper Ions ◽  
Dielectric Strength ◽  
Time Dependent ◽  
Breakdown Field ◽  
Field Range ◽  
Time Dependent Dielectric Breakdown ◽  
Voltage Ramp ◽  
Low K

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.

10 kV, 10 A Bipolar Junction Transistors and Darlington Transistors on 4H-SiC

2010 ◽  
Vol 645-648 ◽  
pp. 1025-1028 ◽  
Author(s):  
Qing Chun Jon Zhang ◽  
Robert Callanan ◽  
Anant K. Agarwal ◽  
Albert A. Burk ◽  
Michael J. O'Loughlin ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Voltage Drop ◽  
Current Gain ◽  
Bipolar Junction Transistors ◽  
Collector Current ◽  
Forward Voltage ◽  
Collector Voltage ◽  
Forward Voltage Drop ◽  
Chip Size ◽  
Dc Current

4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.

Electron Tunneling Current in an n-p-n Bipolar Transistor Based on Armchair Graphene Nanoribbon by Using Airy-Wavefunction Approach

2015 ◽  
Vol 1112 ◽  
pp. 80-84
Author(s):  
Fatimah A. Noor ◽  
Rifky Syariati ◽  
Endi Suhendi ◽  
Mikrajuddin Abdullah ◽  
Khairurrijal
Keyword(s):  
Electron Tunneling ◽  
Tunneling Current ◽  
Band Gap Energy ◽  
Graphene Nanoribbon ◽  
Bipolar Transistor ◽  
Electron Effective Mass ◽  
Collector Voltage ◽  
Armchair Graphene Nanoribbon ◽  
Armchair Graphene ◽  
Emitter Voltage

We have developed a model of the tunneling current in n-p-n bipolar transistor based on armchair graphene nanoribbon (AGNR). Airy-wavefunction approach is employed to obtain electron transmittance, and the obtained transmittance is then used to obtain the tunneling current. The tunneling current is calculated for various variables such as base-emitter voltage, base-current voltage, and AGNR width. It is found that the tunneling current increases with increasing the base-emitter voltage or the base-collector voltage. This result is due to the lowered barrier height of the base region caused by the increase in the base-emitter voltage or the base-collector voltage. In addition, the tunneling current density increases with the width for narrow AGNR and, on the other hand, it decreases for wide AGNR. This finding might be due to the contributions of the band gap energy and the electron effective mass of AGNR which are inversely proportional to the AGNR width.

A Relaxation Corrected Voltage Ramp Stress Measurement for Fast Wafer Level Reliability

2016 ◽  
Vol 16 (11) ◽  
pp. 11133-11136
Author(s):  
Dong-Hwi Lee ◽  
Hyun-Jun Bang ◽  
Manh-Cuong Nguyen ◽  
An Hoang Thuy Nguyen ◽  
Sol Kang ◽  
...  
Keyword(s):  
Stress Measurement ◽  
Wafer Level ◽  
Voltage Ramp

SHORT LOOP ELECTRICAL AND RELIABILITY LEARNING FOR THROUGH SILICON VIA (TSV)MID-WAFER FRONT-SIDE PROCESSES

2014 ◽  
Vol 2014 (1) ◽  
pp. 000794-000803 ◽  
Author(s):  
Victor Vartanian ◽  
Klaus Hummler ◽  
Steve Olson ◽  
Tyler Barbera ◽  
Kai-Hung Yu ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
High Volume ◽  
Front Side ◽  
Wafer Level ◽  
Metal Line ◽  
Through Silicon Via ◽  
Fully Integrated ◽  
Short Loop ◽  
Voltage Ramp ◽  
Reliability Assessments

Even as unit processes for high aspect ratio (HAR) through silicon via (TSV) mid-wafer front-side processing are becoming relatively mature, scaling of the TSVs and reduction of cost of ownership (COO) drive significant innovations in processes, equipment and materials. To assess their high volume manufacturing (HVM) worthiness, any new unit processes need to be evaluated with respect to yield, reliability and COO. Fully integrated product runs tend to be too slow and expensive for this purpose. At SEMATECH, we use TSV mid-wafer short loop test vehicles for rapid learning cycles through in-line electrical test (ILT) and wafer-level reliability assessments using voltage ramp dielectric breakdown (VRDB). These test vehicles contain 5 × 50 μm or 2 × 40 μm TSV comb test structures, which are testable after the first front-side metal line layer level. Novel unit processes by our associate member companies are inserted into the process flow, and are optimized and assessed using split lot experiments. Processes including TSV etch, post TSV etch cleans, dielectric liner deposition, Cu diffusion barrier and seed deposition, as well as TSV fill by Cu electrochemical deposition (ECD) were evaluated. ILT and VRDB results for short loop lots are presented and discussed.

Sequential activation of multiple persistent inward currents induces staircase currents in serotonergic neurons of medulla in ePet-EYFP mice

2020 ◽  
Vol 123 (1) ◽  
pp. 277-288
Author(s):  
Yi Cheng ◽  
Qiang Zhang ◽  
Yue Dai
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Spinal Neurons ◽  
Serotonergic Neurons ◽  
Persistent Inward Currents ◽  
Functional Roles ◽  
Bath Application ◽  
Voltage Ramp ◽  
Inward Currents ◽  
Sequential Activation

Persistent inward currents (PICs) are widely reported in rodent spinal neurons. A distinctive pattern observed recently is staircase-like PICs induced by voltage ramp in serotonergic neurons of mouse medulla. The mechanism underlying this pattern of PICs is unclear. Combining electrophysiological, pharmacological, and computational approaches, we investigated the staircase PICs in serotonergic neurons of medulla in ePet-EYFP transgenic mice (postnatal days 1–7). Staircase PICs induced by 10-s voltage biramps were observed in 70% of serotonergic neurons ( n = 73). Staircase PICs activated at −48.8 ± 5 mV and consisted of two components, with the first PIC of 45.8 ± 51 pA and the second PIC of 197.3 ± 126 pA ( n = 51). Staircase PICs were also composed of low-voltage-activated sodium PIC (Na-PIC; onset −46.2 ± 5 mV, n = 34), high-voltage-activated calcium PIC (Ca-PIC; onset −29.3 ± 6 mV, n = 23), and high-voltage-activated tetrodotoxin (TTX)- and dihydropyridine-resistant sodium PIC (TDR-PIC; onset −16.8 ± 4 mV, n = 28). Serotonergic neurons expressing Na-PIC, Ca-PIC, and TDR-PIC were evenly distributed in medulla. Bath application of 1–2 μM TTX blocked the first PIC and decreased the second PIC by 36% ( n = 23, P < 0.05). Nimodipine (25 μM) reduced the second PIC by 38% ( n = 34, P < 0.001) without altering the first PIC. TTX and nimodipine removed the first PIC and reduced the second PIC by 59% ( n = 28, P < 0.01). A modeling study mimicked the staircase PICs and verified experimental conclusions that sequential activation of Na-PIC, Ca-PIC, and TDR-PIC in order of voltage thresholds induced staircase PICs in serotonergic neurons. Further experimental results suggested that the multiple components of staircase PICs play functional roles in regulating excitability of serotonergic neurons in medulla. NEW & NOTEWORTHY Staircase persistent inward currents (PICs) are mediated by activation of L-type calcium channels in dendrites of mouse spinal motoneurons. A novel mechanism is explored in this study. Here we report that the staircase PICs are mediated by sequentially activating sodium and calcium PICs in serotonergic neurons of mouse medulla.

scholarly journals Metallized ceramic substrate with mesa structure for voltage ramp-up of power modules

2019 ◽  
Vol 87 (2) ◽  
pp. 20903 ◽  
Author(s):  
Hélène Hourdequin ◽  
Lionel Laudebat ◽  
Marie-Laure Locatelli ◽  
Zarel Valdez-Nava ◽  
Pierre Bidan
Keyword(s):  
Field Enhancement ◽  
Wide Bandgap ◽  
Ceramic Substrate ◽  
Electrical Insulation ◽  
Shape Modification ◽  
Mesa Structure ◽  
Power Modules ◽  
Voltage Ramp ◽  
Bandgap Semiconductors ◽  
Semiconductor Chips

As the available wide bandgap semiconductors continuingly increase their operating voltages, the electrical insulation used in their packaging is increasingly constrained. More precisely the ceramic substrate, used in demanding applications, represents a key multi-functional element is being in charge of the mechanical support of the metallic track that interconnects the semiconductor chips with the rest of the power system, as well as of electrical insulation and of thermal conduction. In this complex assembly, the electric field enhancement at the triple junction between the ceramic, the metallic track borders and the insulating environment is usually a critical point. When the electrical field at the triple point exceeds the critical value allowed by the insulation system, this hampers the device performance and limits the voltage rating for future systems. The solution proposed here is based on the shape modification of the ceramic substrate by creating a mesa structure (plateau) that holds the metallic tracks in the assembly. A numerical simulation approach is used to optimize the structure. After the elaboration of the structures by ultrasonic machining we observed a significant increase (30%) in the partial discharge detection voltages, at 10 pC sensitivity, in a substrate with a mesa structure when comparing to a conventional metallized ceramic substrate.

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