On the Determination of the Chip Nozzle Recognition System by Using Machine Vision

To solve the problem of chip damage caused by the using the wrong type of vacuum nozzle during the packaging of semiconductor chips. A recognition system of vacuum nozzle based on machine vision was proposed. In this research, 29 kinds of lifting nozzles are selected as test samples. The backlight intensity of two lifting nozzle images (one strong and one weak separately) is collected at the first beginning. Then, the Blob analysis method is using to analyze the weak backlighting image. The area of the lifting nozzle and the minimum outer rectangular feature can be obtained subsequently. To identify the shape of the liftin nozzle (round or square), the area ratio is calculated. At the same time, the minimum outer rectangular of the lifting nozzle is selected as the reference rectangle. Then, construct the measurement rectangle. The 2-dimensional size of the lifting nozzle is measured as well. Meanwhile, for the strong backlight image, the average value of the grayscale which located within the minimum outer rectangle is calculated. Therefore, the color (black, white, or beige) of the nozzle can be identified. Finally, the sample data is saved to the database as the sample database. During the recognition process, the shape, color, and size of the lifting nozzle being analyzing are using as the parameter to realize the condition inquire. The experimental results show that the recognition accuracy of this method is 98.85%, and the recognition time of one nozzle is around 1 second, which meets the requirements of practical application.

Rapid 3D-Imaging of Semiconductor Chips Using THz Time-of-Flight Technique

In this study, we developed a rapid three-dimensional (3D) time-of-flight imaging tool for inspection of packaged semiconductor chips, using terahertz (THz) time-domain spectroscopy techniques. A high-speed THz system based on the optical sampling by cavity tuning technique is incorporated with a 2-axis galvano scanner to deliver a scanning speed of more than 100 Hz/pixel with a signal-to-noise ratio larger than 20 dB. Through the use of the Hilbert transformation, we reconstruct the 3D structure of the packaged chip in a nondestructive manner. Additionally, the use of frequency-selective imaging allows us to manipulate image resolution; the higher resolution was obtained when monitored using the higher frequency component. Further, using phase information, we were able to detect and identify defects in the packaged chip, such as the delamination area and epoxy-rich regions.

SLLB-DEVS: An Approach for DEVS Based Modeling of Semiconductor Lithography Load Balance

In industrial applications, software related to computational lithography using a DP system method, which refers to how efficiently hardware resources are used, has a significant impact on performance. Because the amount of data to be processed per unit of time is comparatively large in the current semiconductor industry, the efficiency of hardware should be increased through job 12 scheduling by using the most efficient load balancing techniques possible. For efficient scheduling of the load balancer, these are necessary to predict the end time of a given job; this is calculated based on the performance of computing resources and the development of effective traffic distribution algorithms. Due to the high integration of semiconductor chips, the volume of mask exposure data has increased exponentially, the number of slave nodes is increasing, and most EDA tools require one license per DP node to perform a simulation. In this paper, in order to improve efficiency and reduce cost through more efficient load balancing scheduling, a new type of DEVS load balancing method was studied based on the existing industrial E-beam cluster model. The designed DEVS model showed up to four times the throughput of the existing legacy model for medium and large clusters when the BSF policy was applied.

Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion

Cellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity, cascadability, and locality of interconnections confined to neighboring logic cells. However, this outcome is not easily transferable to tree-structured CA, since the neighbors having half and double the index value of the current CA cell under question can be sufficiently distanced apart on the FPGA floor. Challenges to meet throughput requirements, seamlessly translate algorithmic modifications for changing application specifications to gate level architectures and to address reliability challenges of semiconductor chips are ever increasing. Thus, a proper design framework assisting automation of synthesizable, delay-optimized VLSI architecture descriptions facilitating testability is desirable. In this article, we have automated the generation of hardware description of tree-structured CA that includes a built-in scan path realized with zero area and delay overhead. The scan path facilitates seeding the CA, state modification, and fault localization on the FPGA fabric. Three placement algorithms were proposed to ensure maximum physical adjacency amongst neighboring CA cells, arranged in a multi-columnar fashion on the FPGA grid. Our proposed architectures outperform implementations arising out of standard placers and behavioral designs, existing tree mapping strategies, and state-of-the-art FPGA centric error detection architectures in area and speed.

Securing Semiconductor Supply Chains

The countries with the greatest capacity to develop, produce and acquire state-of-the-art semiconductor chips hold key advantages in the development of emerging technologies. At present, the United States and its allies possess significant leverage over core segments of the supply chain used to produce these chips. This policy brief outlines actions the United States and its allies can take to secure that advantage in the long term and use it to promote the beneficial use of emerging technologies, such as artificial intelligence.

A New Core Level Utilization Algorithm for Energy-Efficient Multicore Systems

The energy consumption is becoming a constraint on all computer devices, from smartphones to supercomputers. Consequently, the focus has moved from performance to energy and power consumption. Design metrics are not only based solely on performance, as the energy performance of application executions is becoming the main aspect of architecture. Also, Design metrics depend on, the manufacturers of semiconductor chips which, have implemented multicore processors to boost the level of energy efficiency by using verified techniques for voltage and frequency scaling. To utilize the maximum potential of such architectures, we need to make the right decisions because parameters such as core type, frequency, and utilization typically affect power dissipation and performance. This paper proposes a new algorithm to achieve energy-efficient by monitoring core energy and level utilization control such as: Increasing the number of cores to execute the task, scaling voltage, and frequency. Based on the built model, we analyze the energy efficiency variations for different platform configurations providing the same level of performance. We show that trading the number and type of core with frequency and voltage level and core utilization rate can lead to substantial energy efficiency gains.

Effects of He/H2 Plasma Treatment on Properties of SiCOH Films Deposited with the 1,1,1,3,5,7,7,7- Octamethyl-3,5-Bis(Trimethylsiloxy) Tetrasiloxane Precursor

Low-dielectric-constant SiCOH films fabricated using plasma enhanced chemical vapor deposition (PECVD) are widely used as inter-metallic dielectric (IMD) layers in interconnects of semiconductor chips. In this work, SiCOH films were deposited with 1,1,1,3,5,7,7,7-octamethyl-3,5-bis(trimethylsiloxy)tetrasiloxane (OMBTSTS), and plasma treatment was performed by an inductively coupled plasma (ICP) system with mixture of He and H2. The values of relative dielectric constant (k) of the as-deposited SiCOH films ranged from 2.64 to 4.19. The He/H2 plasma treatment led to a reduction of the k values of the SiCOH films from 2.64–4.19 to 2.07–3.94. To investigate the impacts of the He/H2 plasma treatment on the SiCOH films, the chemical compositions and structures of the as-deposited and treated the SiCOH films were compared by Fourier transform infrared spectroscopy. The experimental results indicate that the k value of the SiCOH films was decreased, there was a proportional increase in pore-related Si–O–Si structure, which is commonly called the cage structure with lager angle than 144°, after He/H2 plasma treatment. The He/H2 plasma treatment was considered to have reduced the k value by forming pores that could be represented by the cage structure. On the other hand, the leakage current density of the SiCOH films was slightly degraded by He/H2 plasma treatment, however, this was tolerable for IMD application. Concludingly the He/H2 plasma treated SiCOH film has the lowest relative dielectric constant (k~2.08) when the most highly hydrocarbon removal and cage structure formation increased.