Formation of thin Ni2Si and NiSi films using low temperature rapid thermal processing

2009 ◽  
Author(s):  
J.P. Li ◽  
Aaron Hunter ◽  
Rajesh Ramanujam ◽  
Michael Liu ◽  
Norman Tam ◽  
...  
Keyword(s):  
Low Temperature ◽  
Thermal Processing ◽  
Rapid Thermal Processing

Low temperature shallow junction formation using vacuum ultraviolet photons during rapid thermal processing

1997 ◽  
Vol 70 (13) ◽  
pp. 1700-1702 ◽  
Author(s):  
R. Singh ◽  
K. C. Cherukuri ◽  
L. Vedula ◽  
A. Rohatgi ◽  
S. Narayanan
Keyword(s):  
Low Temperature ◽  
Thermal Processing ◽  
Vacuum Ultraviolet ◽  
Rapid Thermal Processing ◽  
Shallow Junction ◽  
Junction Formation ◽  
Ultraviolet Photons

Gas Flow Engineering in Rapid Thermal Processing

1994 ◽  
Vol 342 ◽  
Author(s):  
Z. Nényei ◽  
H. Sommer ◽  
J. Gelpey ◽  
A. Bauer
Keyword(s):  
Low Temperature ◽  
Thermal Processing ◽  
Gas Dynamics ◽  
Silicon Surface ◽  
Gas Flow ◽  
Rapid Thermal Processing ◽  
Inert Gas ◽  
Guard Ring ◽  
Interface Damage ◽  
Bottom Heater

ABSTRACTGas flow engineering involves gas dynamics optimization for effective ambient change before heating and for homogeneous convective cooling of the wafers during the heating steps. Multiple gas buffle system, dynamical gas handling, low pressure operation, low temperature edge guard ring and independent top and bottom heater bank control are the proper tools for this optimization. Silicon surface or interface damage during inert gas anneal can be avoided by addition of a small amount of oxygen.

scholarly journals Low Temperature Ni-Al Ohmic Contacts to p-Type 4H-SiC Using Semi-Salicide Processing

2018 ◽  
Vol 924 ◽  
pp. 389-392 ◽  
Author(s):  
Mattias Ekström ◽  
Shuoben Hou ◽  
Hossein Elahipanah ◽  
Arash Salemi ◽  
Mikael Östling ◽  
...  
Keyword(s):  
Low Temperature ◽  
Ohmic Contact ◽  
Thermal Processing ◽  
Ohmic Contacts ◽  
Rapid Thermal Processing ◽  
Nickel Silicide ◽  
Second Step ◽  
Low Resistance ◽  
Annealing Step ◽  
P Type

Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.

Effects of Wafer Backside Emissivity Variation and System Control for Low Temperature Applications

1989 ◽  
Vol 146 ◽  
Author(s):  
Jay J. Pelletier ◽  
Thomsa E. Winter
Keyword(s):  
Low Temperature ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Nonlinear Effects ◽  
Processing Technology ◽  
System Control ◽  
Wafer Temperature ◽  
Lamp Current ◽  
Current Monitoring ◽  
Temperature Applications

ABSTRACTRapid thermal processing technology is being investigated for many uses such as shallow junction diffusion and implant annealing. Most of these processes are done at temperatures above 700 C. It is desirable to use the rapid thermal processor for some low temperature applications such as hillock reduction because of the systems ability to heat up and cool down almost instantaneously as compared to conventional furnaces. Machine control for low temperature processing is more difficult than high temperature processing dur to the optical pyrometers inability to perform at its lower limit. Well documented nonlinear effects of wafer backside emissivity over a temperature range of 400C to 600C will also contribute to wafer to wafer temperature instability. In order to fully utilize the advantages of rapid thermal processing technology, it is imperative that the RTPs performance and repeatability at low temperatures be understood.This paper will discuss the effect of wafer to wafer backside emissivity differences on wafer temperature for low temperature applications. Typical wafer to wafer backside emissivity variation is presented as well as the measurement error of the Peak “ACE” system. “ACE” (Automatic Compensation for Emissivity) can be used to correct for emissivity differences from wafer to wafer.Effect of improper emissivity selection on actual wafer temperature is presented. Also actual wafer temperature sensitivity to changes in programmed temperature with constant, uncompensated emissivity is demonstrated.Lamp current monitoring is discussed with supporting data to show the ability of it to be used as a day to day monitor of system performance. Also, The effects of lamp problems associated with idle current.

Ultra Low Thermal Budget Rapid Thermal Processing for Thin Gate Oxide Dielectrics: Reduction of Suboxide Transition Regions in Low Temperature Processed Si/SiO2 Structures by A 900°C 30 Second Rapid Thermal Anneal

1997 ◽  
Vol 470 ◽  
Author(s):  
G. Lucovsky ◽  
B. Hinds
Keyword(s):  
Low Temperature ◽  
Thermal Processing ◽  
Gate Dielectric ◽  
Rapid Thermal Processing ◽  
Rapid Thermal Anneal ◽  
Thermal Budget ◽  
Kinetic Effects ◽  
C 30 ◽  
Thin Gate Oxide ◽  
Low Thermal Budget

ABSTRACTDevice quality gate dielectric heterostructures have been prepared using a three step plasma/rapid thermal sequence [1] in which kinetic effects determine the time-temperature aspects of the processing. The steps for forming the interface and for depositing dielectric layers have been performed at low temperature, ∼300°C, by plasma-assisted processing. Following this a low rapid thermal anneal (RTA) provides interface and bulk dielectric chemical and structural relaxations, thereby yielding device performance and reliability essentially the same as obtained using higher thermal budget conventional or rapid thermal processing.

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