Low-voltage vibration sensor in standard CMOS process

2007 ◽  
Author(s):  
Benxian Peng ◽  
Ting Yu ◽  
Fengqi Yu
Keyword(s):  
Low Voltage ◽  
Vibration Sensor ◽  
Cmos Process ◽  
Standard Cmos Process

ULTRA-LOW-VOLTAGE GAIN-ENHANCED FOUR-PHASE CHARGE PUMP WITHOUT BODY EFFECT

2014 ◽  
Vol 23 (07) ◽  
pp. 1450104 ◽  
Author(s):  
CHANGLONG LIN ◽  
XINZHUO SUN ◽  
SHILIANG MA ◽  
XIN LU ◽  
KE LIANG ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
The Body ◽  
Cmos Process ◽  
Resistive Load ◽  
Voltage Gain ◽  
Body Effect ◽  
Charge Pumps ◽  
Standard Cmos Process

In this paper, an ultra-low-voltage gain-enhanced four-phase charge pump is proposed. The proposed charge pump is designed in 0.18 μm 1.8 V standard CMOS process with high voltage boosting efficiency when the supply voltage is between 0.5 V and 1.8 V. Moreover, it eliminates the body effect by means of adding two auxiliary substrate switching PMOS transistor. The simulation results show that the proposed charge pump has higher efficiency than the other two low voltage charge pumps when the resistive load is 100 M ohm and the supply voltage is between 0.5 and 1.8 V. A test chip has been realized in a 0.18 μm 1.8 V standard CMOS process. The test results show perfect performance when the supply voltage is between 0.7 and 1.8 V. The proposed charge pump is quite suitable for low power applications.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

Fabrication of Monolithic Integrated Bimaterial Resonant Uncooled IR Sensor

2013 ◽  
Vol 543 ◽  
pp. 176-179 ◽  
Author(s):  
D.Q. Zhao ◽  
Xia Zhang ◽  
P. Liu ◽  
F. Yang ◽  
C. Lin ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Hole Mobility ◽  
Micro Electro Mechanical System ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Ir Sensor ◽  
Cantilever Structure ◽  
Cmos Mems ◽  
On Chip ◽  
Micro Cantilever

In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

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