Considerations for Neuromorphic Supercomputing in Semiconducting and Superconducting Optoelectronic Hardware

Any large-scale spiking neuromorphic system striving for complexity at the level of the human brain and beyond will need to be co-optimized for communication and computation. Such reasoning leads to the proposal for optoelectronic neuromorphic platforms that leverage the complementary properties of optics and electronics. Starting from the conjecture that future large-scale neuromorphic systems will utilize integrated photonics and fiber optics for communication in conjunction with analog electronics for computation, we consider two possible paths toward achieving this vision. The first is a semiconductor platform based on analog CMOS circuits and waveguide-integrated photodiodes. The second is a superconducting approach that utilizes Josephson junctions and waveguide-integrated superconducting single-photon detectors. We discuss available devices, assess scaling potential, and provide a list of key metrics and demonstrations for each platform. Both platforms hold potential, but their development will diverge in important respects. Semiconductor systems benefit from a robust fabrication ecosystem and can build on extensive progress made in purely electronic neuromorphic computing but will require III-V light source integration with electronics at an unprecedented scale, further advances in ultra-low capacitance photodiodes, and success from emerging memory technologies. Superconducting systems place near theoretically minimum burdens on light sources (a tremendous boon to one of the most speculative aspects of either platform) and provide new opportunities for integrated, high-endurance synaptic memory. However, superconducting optoelectronic systems will also contend with interfacing low-voltage electronic circuits to semiconductor light sources, the serial biasing of superconducting devices on an unprecedented scale, a less mature fabrication ecosystem, and cryogenic infrastructure.

Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.