Applications of Wireless Communication in a New Dual Branch CTS Charge Pump Based on Employing Clock Matched Technology

With the increase in communication requirements, new communication technologies and implementation methods have developed rapidly. The rise of emerging markets such as the Internet of Things, smart homes, smart cities, and wearables has promoted the development of wireless communication integrated circuits in the direction of monolithic, low energy consumption, and high energy efficiency. This paper proposes a new dual branch charge pump based on CTS charge pump with enhanced current drive capability and undesired charge transfer completely eliminated. Clock matched technology is proposed to completely eliminate undesired charge transfer caused by delay turn on and off of the auxiliary transistors in the traditional CTS charge pump. The current drive capability is enhanced by employing NMOS transistors with 2Vdd gate drive voltage, while traditional dual branch CTS charge pumps are based on PMOS with 1Vdd gate drive voltage. The output voltage ripple is also reduced resulting from a dual branch structure. Simulation results of output voltage gain and power efficiency for the proposed charge pump and other traditional charge pumps are provided. Comparisons are made to show the improvement of the proposed charge pump compared with other traditional charge pumps.

A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

This paper presents two variants of a high step-up ratio charge pump for high voltage micro electro-mechanical system and condenser microphones. The implementations are based on an additive charge pump topology where respectively 46 and 57 cascaded stages are used to generate an output voltage of 182 V from a supply voltage of 5 V. The two charge pumps have been fabricated in a 180 nm SOI process with a breakdown voltage of more than 200 V and respectively occupy an area of 0.52 mm2 and 0.39 mm2. The charge pumps can output up to 182.5 V and 181.7 V and are designed to drive a capacitive load with a leakage of 2 nA. When driven with a 100 kHz clock, their power consumption is respectively 40 µW and 20 µW. The rise time of the charge pumps output from 0 V to 182 V is less than 5 ms. The implemented charge pumps exhibit state-of-the-art performance for very high voltage dc-dc capacitive drive applications.

Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS

This paper proposes a comparative study of regulation schemes for charge-pump-based voltage generators using behavioral models in Verilog- Analog Mixed Signal (AMS) code. An accurate and simple model of the charge pump is first introduced. It allows reducing the simulation time of complex electronic systems made up by both analog and digital circuits while maintaining a good agreement with transistor-level simulations. Finally, a comprehensive comparative study of the different regulation schemes for charge pumps is reported which allows the designer to choose the most suitable topology for a given application and Charge Pump (CP) operative zone.