Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability

2018 ◽  
Vol 39 (1) ◽  
pp. 8-11 ◽  
Author(s):  
Jer-Yi Lin ◽  
Malkundi Puttaveerappa Vijay Kumar ◽  
Tien-Sheng Chao
Keyword(s):  
Gate Bias ◽  
Electrical Characteristics ◽  
Bias Stress ◽  
Gate Bias Stress

Effects of Gate Bias Stress on the Electrical Characteristics of ZnO Thin Film Transistor

2008 ◽  
Vol 53 (1) ◽  
pp. 412-415 ◽  
Author(s):  
Jae-Hong Jeon ◽  
Hee-Hwan Choe ◽  
Kang-Woong Lee ◽  
Jae-Heon Shin ◽  
Chi-Sun Hwang ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Zno Thin Film ◽  
Gate Bias ◽  
Electrical Characteristics ◽  
Bias Stress ◽  
Gate Bias Stress

P-6.1: Asymmetric Effects of Gate-Bias Stress Voltage on the Stability under Positive and Negative Gate-Bias Stress of a-IGZO TFTs

2018 ◽  
Vol 49 ◽  
pp. 597-600
Author(s):  
Xiaoliang Zhou ◽  
Xiaodong Zhang ◽  
Yang Shao ◽  
Letao Zhang ◽  
Hongyu He ◽  
...  
Keyword(s):  
Gate Bias ◽  
Asymmetric Effects ◽  
Bias Stress ◽  
The Stability ◽  
Stress Voltage ◽  
Gate Bias Stress

Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor

2011 ◽  
Vol 99 (2) ◽  
pp. 022104 ◽  
Author(s):  
Te-Chih Chen ◽  
Ting-Chang Chang ◽  
Tien-Yu Hsieh ◽  
Wei-Siang Lu ◽  
Fu-Yen Jian ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Bias Stress ◽  
Trapping Effect ◽  
Gate Bias Stress

Degradation behavior and degradation mechanism of bridged-grain polycrystalline silicon thin film transistors under AC gate bias stress

2017 ◽  
Vol 32 (2) ◽  
pp. 91-96
Author(s):  
张猛 ZHANG Meng ◽  
夏之荷 XIA Zhi-he ◽  
周玮 ZHOU Wei ◽  
陈荣盛 CHEN Rong-sheng ◽  
王文 WONG Man ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Degradation Mechanism ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Silicon Thin Film ◽  
Bias Stress ◽  
Gate Bias Stress

Investigation of the threshold voltage drift in enhancement mode GaN MOSFET under negative gate bias stress

2015 ◽  
Vol 54 (4) ◽  
pp. 044101 ◽  
Author(s):  
Fei Sang ◽  
Maojun Wang ◽  
Chuan Zhang ◽  
Ming Tao ◽  
Bing Xie ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Bias ◽  
Bias Stress ◽  
Enhancement Mode ◽  
Voltage Drift ◽  
Gate Bias Stress

scholarly journals Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

Energies ◽  
2020 ◽  
Vol 13 (10) ◽  
pp. 2628 ◽  
Author(s):  
Surya Elangovan ◽  
Stone Cheng ◽  
Edward Yi Chang
Keyword(s):  
Gallium Nitride ◽  
Rise Time ◽  
High Stress ◽  
High Electron Mobility Transistor ◽  
Interface State ◽  
High Electron ◽  
Gate Bias ◽  
Bias Stress ◽  
Turn On ◽  
Gate Bias Stress

We present a detailed study of dynamic switching instability and static reliability of a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High-Electron-Mobility-Transistor (MIS-HEMT) based cascode switch under off-state (negative bias) Gate bias stress (VGS, OFF). We have investigated drain channel current (IDS, Max) collapse/degradation and turn-on and rise-time (tR) delay, on-state resistance (RDS-ON) and maximum transconductance (Gm, max) degradation and threshold voltage (VTH) shift for pulsed and prolonged off-state gate bias stress VGS, OFF. We have found that as stress voltage magnitude and stress duration increases, similarly IDS, Max and RDS-ON degradation, VTH shift and turn-on/rise time (tR) delay, and Gm, max degradation increases. In a pulsed off-state VGS, OFF stress experiment, the device instabilities and degradation with electron trapping effects are studied through two regimes of stress voltages. Under low stress, VTH shift, IDS collapse, RDS-ON degradation has very minimal changes, which is a result of a recoverable surface state trapping effect. For high-stress voltages, there is an increased and permanent VTH shift and high IDS, Max and RDS-ON degradation in pulsed VGS, Stress and increased rise-time and turn-on delay. In addition to this, a positive VTH shift and Gm, max degradation were observed in prolonged stress experiments for selected high-stress voltages, which is consistent with interface state generation. These findings provide a path to understand the failure mechanisms under room temperature and also to accelerate the developments of emerging GaN cascode technologies.

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