Low-Frequency Noise in Enhancement-Mode GaN MOS-HEMTs by Using Stacked $\hbox{Al}_{2}\hbox{O}_{3}/\hbox{Ga}_{2}\hbox{O}_{3}/\hbox{Gd}_{2}\hbox{O}_{3}$ Gate Dielectric

2012 ◽  
Vol 33 (7) ◽  
pp. 958-960 ◽  
Author(s):  
Hsien-Chin Chiu ◽  
Jia-Hsuan Wu ◽  
Chih-Wei Yang ◽  
Fan-Hsiu Huang ◽  
Hsuan-Ling Kao
2009 ◽  
Vol 105 (12) ◽  
pp. 124504 ◽  
Author(s):  
S. L. Rumyantsev ◽  
Sung Hun Jin ◽  
M. S. Shur ◽  
Mun-Soo Park

2009 ◽  
Vol 30 (5) ◽  
pp. 523-525 ◽  
Author(s):  
Hyun-Sik Choi ◽  
Seung-Ho Hong ◽  
Rock-Hyun Baek ◽  
Kyong-Taek Lee ◽  
Chang-Yong Kang ◽  
...  

2011 ◽  
Vol 20 (01) ◽  
pp. 105-113
Author(s):  
S. RUMYANTSEV ◽  
W. STILLMAN ◽  
M. SHUR ◽  
T. HEEG ◽  
D.G. SCHLOM ◽  
...  

Insulated gate n-channel enhancement mode InGaAs field effect transistors with the GdScO 3 high-k dielectric have been fabricated and studied. The low frequency noise was high indicating a high interface density of traps. Trap density and its dependence on the gate voltage have been extracted from the noise and conductance measurements.


AIP Advances ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 015219
Author(s):  
E. Simoen ◽  
B. J. O’Sullivan ◽  
N. Ronchi ◽  
G. Van den Bosch ◽  
D. Linten ◽  
...  

2014 ◽  
Vol 778-780 ◽  
pp. 428-431 ◽  
Author(s):  
Lucy Claire Martin ◽  
Hua Khee Chan ◽  
David T. Clark ◽  
Ewan P. Ramsay ◽  
A.E. Murphy ◽  
...  

Low frequency noise in 4H-SiC lateral p-channel metal oxide semiconductor field effect transistors (PMOSFETs) in the frequency range from 1 Hz to 100 kHz has been used to investigate the relationship between gate dielectric fabrication techniques and the resulting density of interface traps at the semiconductor-dielectric interface in order to examine the impact on device performance. The results show that the low frequency noise characteristics in p-channel 4H-SiC MOSFETs in weak inversion are in agreement with the McWhorter model and are dominated by the interaction of channel carriers with interface traps at the gate dielectric/semiconductor interface.


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