24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits

2012 ◽  
Author(s):  
Tadashi Yasufuku ◽  
Koji Hirairi ◽  
Yu Pu ◽  
Yun Fei Zheng ◽  
Ryo Takahashi ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Control ◽  
Logic Circuits ◽  
Power Reduction

Effective Circuit Design Methodologies for Standby Leakage Power Reduction

2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Model Parameters ◽  
Mos Transistor ◽  
Design Methodologies ◽  
Transistor Model

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).

Ultra-Low Power Static Logic Circuits Design in Subthreshold Region

2012 ◽  
Vol 182-183 ◽  
pp. 467-471
Author(s):  
Jie Li ◽  
Zhuang Zhang ◽  
Wei Wei Shan
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Monte Carlo Analysis ◽  
Logic Circuits ◽  
Deep Submicron ◽  
Threshold Region ◽  
Subthreshold Region ◽  
Ultra Low Power ◽  
Noise Margin ◽  
Strong Inversion

As semiconductor technology develops toward very deep submicron or even nanometer, power consumption per unit area increases dramatically. Scaling supply voltage into the subthreshold region provides significant energy reduction in logic circuits. However, low voltage and varies of environmental factors make it a challenge to design subthreshold circuit. This paper presents a method to modify standard cells to function well in subthreshold region. The main factors including process, voltage and temperature variables, noise and mismatch, which have more influence on the performance in the sub-threshold region than the strong inversion region. Typical static logics in the standard library TSMC65nm are analyzed by Monte Carlo analysis method when working in sub-threshold region, to find that logical failures occur to NAND VOL and NOR VOH before modified the sizes. After NAND's size increasing 85% and NOR's 370%, the failure has been eliminated and a good noise margin has been achieved.

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing

2016 ◽  
Vol E99.C (10) ◽  
pp. 1219-1225
Author(s):  
Masahiro ISHIDA ◽  
Toru NAKURA ◽  
Takashi KUSAKA ◽  
Satoshi KOMATSU ◽  
Kunihiro ASADA
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Voltage Control ◽  
Fault Testing ◽  
Power Supply Voltage ◽  
Delay Fault ◽  
Delay Fault Testing

Supply voltage quality in low voltage industrial networks of Estonia

2011 ◽  
Vol 18 (2) ◽  
pp. 102 ◽  
Author(s):  
T Vinnal ◽  
K Janson ◽  
J Järvik ◽  
H Kalda ◽  
T Sakkos
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Industrial Networks ◽  
Voltage Quality

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

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