Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits

2006 ◽  
pp. 350-359 ◽  
Author(s):  
Ji-Yong Jeong ◽  
Gil-Su Kim ◽  
Jong-Pil Son ◽  
Woo-Jin Rim ◽  
Soo-Won Kim
Keyword(s):  
Low Voltage ◽  
Logic Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Digital Logic ◽  
Body Bias

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

Effective Circuit Design Methodologies for Standby Leakage Power Reduction

2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Model Parameters ◽  
Mos Transistor ◽  
Design Methodologies ◽  
Transistor Model

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).

SPINTRONIC DEVICES AND CIRCUITS FOR LOW-VOLTAGE LOGIC

2012 ◽  
Vol 21 (01) ◽  
pp. 1250005 ◽  
Author(s):  
DANIEL H. MORRIS ◽  
DAVID M. BROMBERG ◽  
JIAN-GANG (JIMMY) ZHU ◽  
LARRY PILEGGI
Keyword(s):  
Low Voltage ◽  
Logic Gates ◽  
Logic Circuits ◽  
Low Energy ◽  
Digital Logic ◽  
Spintronic Devices ◽  
Magnetic Devices ◽  
Logic Level

This paper describes the design of digital logic circuits composed exclusively from magnetic devices. The logic level of a signal is embedded in the direction of steered currents, not voltages. The currents are steered by small (e.g., 2-3x) resistance changes. Sub-100 mV pulsed voltages power and synchronize the circuits. Logic gates are non-volatile, allowing for fully-pipelined logic that can achieve ultra-low energy for design examples.

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