12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

Author(s):  
Atsushi Muramatsu ◽  
Tadashi Yasufuku ◽  
Masahiro Nomura ◽  
Makoto Takamiya ◽  
Hirofumi Shinohara ◽  
...  
2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).


2016 ◽  
Vol E99.C (10) ◽  
pp. 1219-1225
Author(s):  
Masahiro ISHIDA ◽  
Toru NAKURA ◽  
Takashi KUSAKA ◽  
Satoshi KOMATSU ◽  
Kunihiro ASADA

2015 ◽  
Vol 821-823 ◽  
pp. 910-913 ◽  
Author(s):  
Luigia Lanni ◽  
Bengt Gunnar Malm ◽  
Mikael Östling ◽  
Carl Mikael Zetterling

Integrated digital circuits, fabricated in a bipolar SiC technology, have been successfully tested up to 600 °C. Operated with-15 V supply voltage from 27 up to 600 °C OR-NOR gates exhibit stable noise margins of about 1 or 1.5 V depending on the gate design, and increasing delay-power consumption product in the range 100 - 200 nJ. In the same temperature range an oscillation frequency of about 1 MHz is also reported for an 11-stage ring oscillator.


Author(s):  
Sven Luetkemeier ◽  
Thorsten Jungeblut ◽  
Mario Porrmann ◽  
Ulrich Rueckert

Author(s):  
K. Akynin ◽  
◽  
O. Antonov ◽  
V. Kireiev ◽  
◽  
...  

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