13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO
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2016 ◽
Vol E99.C
(10)
◽
pp. 1219-1225
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2011 ◽
Vol E94-C
(6)
◽
pp. 1072-1075
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