Non-electrical-contact LSI failure analysis using non-bias laser terahertz emission microscope

Author(s):  
Kiyoshi Nikawa ◽  
Masatsugu Yamashita ◽  
Toru Matsumoto ◽  
Chiko Otani ◽  
Masayoshi Tonouchi ◽  
...  
2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001343-001357
Author(s):  
George A. Hernandez ◽  
Daniel Martinez ◽  
Stephen Patenaude ◽  
Charles Ellis ◽  
Michael Palmer ◽  
...  

This paper describes the design and fabrication of liquid metal interconnects (vias) for 2.5D and 3D integration. The liquid metal is gallium indium eutectic with a melting temperature of approximately 15.7°C that is introduced into via openings of a silicon interposer. This liquid interconnect technology can be integrated with existing interposer technologies, such as capacitors and traditional (solid metal) through-silicon vias (TSVs). In addition, liquid metal interconnects can better accommodate thermal stresses and provide re-workability in case of chip failure. Our research efforts are focused on the integration of multi-chip modules using liquid metal interconnects. Our study encompasses Direct Current (D.C.) measurements and failure analysis using snake and comb structures at low temperature (10 degrees Kelvin) to slightly above room temperature (300 degrees Kelvin). The snake and comb structure allows us to measure electrical shorts and opens, as well as provide estimates of via yield and allows additional information for determination of possible failure mechanisms. In order to make electrical contact to the liquid metal interconnect interposer from both the top and bottom, test coupons have been fabricated with arrays of large numbers of vias. The interposer structure consists of a thin (200 um thick) silicon wafer with via holes filled with liquid metal. The test coupon consists of bottom and top silicon die with a thickness of 500 um. The bottom wafer incorporates a 2 um-thick daisy-chain metallization and 100 um copper tall vias, which are electrically isolated from each other and the underlying Si by patterned AL-X dielectric. The top wafer incorporates an array of 80 um tall, electroplated copper pillars and top daisy-chain metallization. Liquid metal containment mechanisms and structures have also been investigated. In our presentation we will describe the design, fabrication and characterization of this re-workable interposer with liquid metal interconnects. We will present D.C. resistance and X-ray imagery of the liquid metal filled via. In addition, we will provide failure analysis of via yield per chip.


2011 ◽  
Vol 51 (9-11) ◽  
pp. 1624-1631 ◽  
Author(s):  
Kiyoshi Nikawa ◽  
Masatsugu Yamashita ◽  
Toru Matsumoto ◽  
Katsuyoshi Miura ◽  
Yoshihiro Midoh ◽  
...  

2016 ◽  
Vol 82 (3) ◽  
pp. 225-229
Author(s):  
Masatsugu YAMASHITA ◽  
Chiko OTANI ◽  
Toru MATSUMOTO ◽  
Yasunori GOTO ◽  
Masayoshi TONOUCHI ◽  
...  

Author(s):  
Jim B. Colvin ◽  
Anirban Roy

Abstract Low yield was reported for a non-volatile embedded memory array. In one case, the n-channel transistor was observed to exhibit single bit OFF leakage in a 32K array. In another case, there was general leakage observed between drain junctions of neighboring transistors, even though these were isolated by field oxide. The objective of the failure analysis described in this article was to characterize the electrical behavior of the leakage and determine the exact location and cause of the leakage. Focused Ion Beam was used to make electrical contact to drain regions, which lacked a contact for microprobing. Once the electrical parameters were obtained, photoemission analysis was performed with modified probes for higher spatial resolution to pinpoint the leakage path. Finally, scanning capacitance microscopy methods were used to prove the presence of the n-type depletion path. Very clear and positive confirmation of the presence of the parasitic n-type dopant was confirmed.


Author(s):  
Changsoo Jang ◽  
Seungbae Park ◽  
Bill Infantolino ◽  
Lawrence Lehman ◽  
Ryan Morgan ◽  
...  

A failure mechanism of pogo-type probe pin is investigated. A probing tester with actuation capable in three-axes is used to simulate the actual inspection process experimentally. Force required to break in surface oxides and develop electrical contact is measured. Contact resistance history reveals that pins mating to Sn surfaces fail earlier than SnPb surfaces. Through periodic inspection of pin using microprobe/EDS as a function of probing count, the general root cause of pin failure is turned out to be pin tip wear out associated with Sn oxide growth on its surface. The cause of earlier failure of the pin probing matte Sn surface is identified as severe wear out by a rough and abrasive characteristic of matte Sn.


Author(s):  
John R. Devaney

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.


Author(s):  
Evelyn R. Ackerman ◽  
Gary D. Burnett

Advancements in state of the art high density Head/Disk retrieval systems has increased the demand for sophisticated failure analysis methods. From 1968 to 1974 the emphasis was on the number of tracks per inch. (TPI) ranging from 100 to 400 as summarized in Table 1. This emphasis shifted with the increase in densities to include the number of bits per inch (BPI). A bit is formed by magnetizing the Fe203 particles of the media in one direction and allowing magnetic heads to recognize specific data patterns. From 1977 to 1986 the tracks per inch increased from 470 to 1400 corresponding to an increase from 6300 to 10,800 bits per inch respectively. Due to the reduction in the bit and track sizes, build and operating environments of systems have become critical factors in media reliability.Using the Ferrofluid pattern developing technique, the scanning electron microscope can be a valuable diagnostic tool in the examination of failure sites on disks.


Author(s):  
S. G. Ghonge ◽  
E. Goo ◽  
R. Ramesh ◽  
R. Haakenaasen ◽  
D. K. Fork

Microstructure of epitaxial ferroelectric/conductive oxide heterostructures on LaAIO3(LAO) and Si substrates have been studied by conventional and high resolution transmission electron microscopy. The epitaxial films have a wide range of potential applications in areas such as non-volatile memory devices, electro-optic devices and pyroelectric detectors. For applications such as electro-optic devices the films must be single crystal and for applications such as nonvolatile memory devices and pyroelectric devices single crystal films will enhance the performance of the devices. The ferroelectric films studied are Pb(Zr0.2Ti0.8)O3(PLZT), PbTiO3(PT), BiTiO3(BT) and Pb0.9La0.1(Zr0.2Ti0.8)0.975O3(PLZT).Electrical contact to ferroelectric films is commonly made with metals such as Pt. Metals generally have a large difference in work function compared to the work function of the ferroelectric oxides. This results in a Schottky barrier at the interface and the interfacial space charge is believed to responsible for domain pinning and degradation in the ferroelectric properties resulting in phenomenon such as fatigue.


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