Identification and Analysis of Parasitic Depletion Mode Leakage in a Memory Select Transistor

2000 ◽  
Author(s):  
Jim B. Colvin ◽  
Anirban Roy
Keyword(s):  
Failure Analysis ◽  
Spatial Resolution ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Contact ◽  
Electrical Behavior ◽  
Embedded Memory ◽  
Electrical Parameters ◽  
Leakage Path ◽  
Field Oxide

Abstract Low yield was reported for a non-volatile embedded memory array. In one case, the n-channel transistor was observed to exhibit single bit OFF leakage in a 32K array. In another case, there was general leakage observed between drain junctions of neighboring transistors, even though these were isolated by field oxide. The objective of the failure analysis described in this article was to characterize the electrical behavior of the leakage and determine the exact location and cause of the leakage. Focused Ion Beam was used to make electrical contact to drain regions, which lacked a contact for microprobing. Once the electrical parameters were obtained, photoemission analysis was performed with modified probes for higher spatial resolution to pinpoint the leakage path. Finally, scanning capacitance microscopy methods were used to prove the presence of the n-type depletion path. Very clear and positive confirmation of the presence of the parasitic n-type dopant was confirmed.

Identification of an IDDQ Failure Mechanism Using a Variety of Front and Backside Analytical Techniques

2003 ◽  
Author(s):  
Jim Shearer ◽  
Kim Le ◽  
Xiaoyu Yang ◽  
Monty Cleeves ◽  
Al Meeks
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Metal Layer ◽  
Ion Beam ◽  
Photon Emission ◽  
Analytical Techniques ◽  
Cmos Process ◽  
Microscopy Imaging ◽  
Leakage Path ◽  
Dual Beam

Abstract This article presents a case study to solve an IDDQ leakage problem using a variety of failure analysis techniques on a product. The product is fabricated using a 3-metal-layer 0.25 μm CMOS process with the addition of Matrix's proprietary 3-D memory layers. The failure analysis used both top and backside analytical techniques, including liquid crystal, photon emission microscopy from both front and back, dual-beam focused ion beam cross-sectioning, field emission scanning electron microscopy imaging, parallel-lap/passive voltage contrast, microprobing of parallel-lapped samples, and scanning capacitance microscopy. The article discusses how the application of each of the techniques narrowed down the search for this IDDQ leakage path. This leakage path was eliminated using the two corrective actions: The resist is pre-treated prior to ion implantation to produce a consistent resist sidewall profile; and the Nwell boundaries were adjusted in the next Nwell mask revision.

Analysis of DC Failure in Advanced Memory Devices Using Nanoprobing and Scanning Capacitance Microscopy

2007 ◽  
Author(s):  
Jen-Lang Lue ◽  
Chin-Shun Lin ◽  
Atup Chiou ◽  
Hsuen-Cheng Liao ◽  
Hsienwen Liu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Leakage Current ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Doping Profile ◽  
Memory Devices ◽  
Cross Sectional ◽  
Analysis Process ◽  
Leakage Path ◽  
Current Voltage

Abstract This paper discusses the failure analysis process of a DC failure using an in-FIB (Focused Ion Beam) nanoprobing technique with four probes and a scanning capacitance microscope (SCM) in advanced DRAM devices. Current-Voltage (I-V) curves measured by the nanoprobing technique indicate the curve of the failed device is different from that of the normal device. The failed device causes a high leakage current in the test. The cross-sectional 2-D doping profile of SCM verifies the region of the P-Well has shifted to create a leakage path that causes this failure.

A High Resolution TEM Specimen Thinning System

1991 ◽  
Vol 254 ◽  
Author(s):  
R. Clampitt ◽  
G. G. Ross ◽  
M. Phelan ◽  
S. A. Davies
Keyword(s):  
High Resolution ◽  
Failure Analysis ◽  
Spatial Resolution ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Specimen Preparation ◽  
Tem Analysis ◽  
Commercial System ◽  
High Resolution Tem

AbstractImprovements in specimen preparation for TEM analysis are being constantly sought, particularly in the study of microelectronics' materials and in failure analysis of devices. We describe here a compact commercial system capable of thinning (milling) selected regions of a specimen by means of a scanned focused ion beam of sub-micron spatial resolution.

Direct Plan View FIB Liftout for Near-Surface Defect Analysis in TEM

2013 ◽  
Author(s):  
Max L. Lifson ◽  
Carla M. Chapman ◽  
D. Philip Pokrinchak ◽  
Phyllis J. Campbell ◽  
Greg S. Chrisman ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Silicon Germanium ◽  
Focused Ion Beam ◽  
Surface Defects ◽  
Ion Beam ◽  
Misfit Dislocations ◽  
Tem Analysis ◽  
Plan View ◽  
Near Surface ◽  
Straightforward Method

Abstract Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.

Fast Turn-around Failure Analysis of Metal Interconnection Using FIB and LA ICP-MS

2010 ◽  
Author(s):  
Zixiao Pan ◽  
Wei Wei ◽  
Fuhe Li
Keyword(s):  
Failure Analysis ◽  
Inductively Coupled Plasma ◽  
Structural Damage ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Detection Sensitivity ◽  
Chemical Contamination ◽  
Inductively Coupled ◽  
Minimal Sample ◽  
Icp Ms

Abstract This paper introduces our effort in failure analysis of a 200 nm thick metal interconnection on a glass substrate and covered with a passivation layer. Structural damage in localized areas of the metal interconnections was observed with the aid of focused ion beam (FIB) cross-sectioning. Laser ablation inductively coupled plasma mass spectroscopy (LA ICP-MS) was then applied to the problematic areas on the interconnection for chemical survey. LA ICP-MS showed direct evidence of localized chemical contamination, which has likely led to corrosion (or over-etching) of the metal interconnection and the assembly failure. Due to the high detection sensitivity of LA ICP-MS and its compatibility with insulating material analysis, minimal sample preparation is required. As a result, the combination of FIB and LA ICP-MS enabled successful meso-scale failure analysis with fast turnaround and reasonable cost.

Logical-to-Physical Device Navigation using Place-and-Route Data as an Alternative to LVS

2006 ◽  
Author(s):  
Roger Nicholson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Traditional Methods ◽  
Navigation Data ◽  
Use Of Time ◽  
Place And Route ◽  
Physical Layout

Abstract Logical-to-physical device navigation for failure analysis is often used to drive physical probers and focused ion beam tools. Traditional methods of creating navigation data rely upon the use of time consuming Layout-versus-Schematic (LVS) based methods. By using existing place-and-route data, full cross-linked navigation between schematic and physical layout may be achieved in a fraction of the time that it takes for the LVS methods to be used. Place-and-route data offers significantly more information to the analyst than LVS based data.

Layout Overlay Techniques to Improve Failure Analysis

1998 ◽  
Author(s):  
Christian Burmer ◽  
Siegfried Görlich ◽  
Siegfried Pauthner
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
New Technologies ◽  
Ion Beam ◽  
Image Correlation ◽  
Microelectronic Devices ◽  
Overlay Technique ◽  
Correlation Techniques ◽  
Navigation Software ◽  
Image Format

Abstract New layout overlay technique has been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-ìm design rules, chemical mechanical polishing techniques (CMP) and autorouted design techniques. As the new technique is realized as an extension of a standard CAD-navigation software and as it makes use of standard image format "TIFF" for data input, which is available at all modern equipments for failure analysis, these technique can be applied to all modern failure analysis methods. Here examples are given for three areas of application: circuit modification using Focused Ion Beam (FIB), support of preparation for backside inspection and fault localization using emission microscopy.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

High-Throughput, Site-Specific Sample Prep of Ultra-Thin TEM Lamella for Process Metrology and Failure Analysis

2012 ◽  
Author(s):  
Roger Alvis ◽  
Jeff Blackwood ◽  
Sang-Hoon Lee ◽  
Matthew Bray
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Process Monitoring ◽  
High Throughput ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Memory Devices ◽  
Site Specific ◽  
Critical Dimensions ◽  
Tem Lamella

Abstract Semiconductor devices with critical dimensions less than 20nm are now being manufactured in volume. A challenge facing the failure analysis and process-monitoring community is two-fold. The first challenge of TEM sample prep of such small devices is that the basic need to end-point on a feature-of-interest pushes the imaging limit of the instrument being used to prepare the lamella. The second challenge posed by advanced devices is to prepare an artifact-free lamella from non-planar devices such as finFETs as well as from structures incorporating ‘non-traditional’ materials. These challenges are presently overcome in many advanced logic and memory devices in the focused ion beam-based TEM sample preparation processes by inverting the specimen prior to thinning to electron transparency. This paper reports a highthroughput method for the routine preparation of artifact-free TEM lamella of 20nm thickness, or less.

Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology

2004 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Copper Interconnects ◽  
Wet Chemical ◽  
Low K ◽  
Section Analysis

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.

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