The electric field, oxide thickness, time and fluence dependences of trap generation in silicon oxides and their support of the E-model of oxide breakdown

1999 ◽  
Author(s):  
D. Qian ◽  
D.J. Dumin
Keyword(s):  
Electric Field ◽  
Oxide Thickness ◽  
Silicon Oxides ◽  
Oxide Breakdown ◽  
Field Oxide

The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  
Keyword(s):  
Electric Field ◽  
Three Dimensional ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Normal Electric Field ◽  
Surface Electric Field ◽  
Tunneling Behavior ◽  
Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

scholarly journals A Novel MOS-Channel Diode Embedded in a SiC Superjunction MOSFET for Enhanced Switching Performance and Superior Short Circuit Ruggedness

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2619
Author(s):  
Jongwoon Yoon ◽  
Kwangsoo Kim
Keyword(s):  
Electric Field ◽  
Switching Time ◽  
Short Circuit ◽  
Oxide Thickness ◽  
Shielding Effect ◽  
Figures Of Merit ◽  
Switching Performance ◽  
Turn On ◽  
Reverse Recovery Time ◽  
Tcad Simulations

In this study, a novel MOS-channel diode embedded in a SiC superjunction MOSFET (MCD SJ-MOSFET) is proposed and analyzed by means of numerical TCAD simulations. Owing to the electric field shielding effect of the P+ body and the P-pillar, the channel diode oxide thickness (tco) of MCD can be set to very thin while achieving a low maximum oxide electric field (EMOX) under 3 MV/cm. Therefore, the turn-on voltage (VF) of the proposed structure was 1.43 V, deactivating the parasitic PIN body diode. Compared with the SJ-MOSFET, the reverse recovery time (trr) and the reverse recovery charge (Qrr) were improved by 43% and 59%, respectively. Although there is a slight increase in specific on-resistance (RON), the MCD SJ-MOSFET shows very low input capacitance (CISS) and gate to drain capacitance (CGD) due to the reduced active gate. Therefore, significantly improved figures of merit RON × CGD by a factor of 4.3 are achieved compared to SJ-MOSFET. As a result, the proposed structure reduced the switching time as well as the switching energy loss (ESW). Moreover, electro-thermal simulation results show that the MCD SJ-MOSFET has a short circuit withstand time (tSC) more than twice that of the SJ-MOSFET at various DC bus voltages (400 and 600 V).

Dependence of Reliability of Ultrathin Mos Gate Oxides on the Fermi Level Positions at Gate and Substrate

1997 ◽  
Vol 473 ◽  
Author(s):  
Tien-Chun Yang ◽  
Navakanta Bhat ◽  
Krishna C. Saraswat
Keyword(s):  
Electric Field ◽  
Fermi Level ◽  
Breakdown Strength ◽  
Gate Oxide ◽  
High Energy ◽  
Constant Current ◽  
Oxide Breakdown ◽  
Mos Devices ◽  
High Energy Electrons ◽  
Substrate Doping

ABSTRACTWe demonstrate that the reliability of ultrathin (< 10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on the position at the substrate for constant current gate injection (Vg-). The oxide breakdown strength (Qbd) is less for p+ poly-Si gate than for n+ poly-Si gate, but, it is independent of the substrate doping type. The degradation of oxides is closely related to the electric field across the gate oxide, which is influenced by the cathode Fermi level. P+ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field must be higher to give the same injection current density. A higher electric field gives more high energy electrons at the anode, and therefore the damage is more at the substrate interface. Different substrate types cause no effect on the oxide electric field, and as a result, they do not influence the degradation.

Effect of the Field Oxidation Process on the Electrical Characteristics of 6500V 4H-SiC JBS Diodes

2020 ◽  
Vol 1014 ◽  
pp. 144-148
Author(s):  
Ling Sang ◽  
Jing Hua Xia ◽  
Liang Tian ◽  
Fei Yang ◽  
Rui Jin ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Oxide Layer ◽  
Vapor Deposition ◽  
Oxidation Process ◽  
Chemical Vapor ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Field Plate ◽  
Plate Length ◽  
Field Oxide

The effect of the field oxidation process on the electrical characteristics of 6500V 4H-SiC JBS diodes is studied. The oxide thickness and field plate length have an effect on the reverse breakdown voltage of the SiC JBS diode. According the simulation results, we choose the optimal thickness of the oxide layer and field plate length of the SiC JBS diode. Two different field oxide deposition processes, which are plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD), are compared in our paper. When the reverse voltage is 6600V, the reverse leakage current of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 0.7 μA, which is 60% lower than that of PECVD process. When the forward current is 25 A, the forward voltage of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 3.75 V, which is 10% higher than that of PECVD process. There should be a trade-off between the forward and reverse characteristics in the actual high power and high temperature applications.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Improvements on Electrical Properties of Ultra-Thin Silicon Oxides Grown by Microwave Afterglow Oxygen Plasma

1994 ◽  
Vol 347 ◽  
Author(s):  
P. C. Chen ◽  
J. Y. Lin ◽  
H. L. Hwang
Keyword(s):  
Microwave Plasma ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Breakdown Field ◽  
Silicon Oxides ◽  
Oxide Breakdown ◽  
Thin Silicon ◽  
State Densities ◽  
Plasma Annealing

ABSTRACTFundamental characteristics such as the oxide breakdown fields, oxide charges and interface state density of various ultra-thin silicon oxides (≤ 8 nm) grown by microwave plasma afterglow oxidation at low temperatures (400 °C and 600 °C) were investigated. The effective Oxide charge density of 600 °C as-grown oxide was as low as 6×1010 cm-2. The breakdown fields of the oxides were further enhanced and the interface state densities were reduced by employing fluorination (HF soaked) and low temperature N2O plasma annealing. The breakdown field of the thin oxide grown at 600 °C with 15 min N2O plasma annealing was 12 MV/cm. The reduction of interface state density was about 35% for 600 °C fluorinated oxide. When integrated with poly-gate process, the interface state density was as low as 5×1010 cm-2eV-1.

scholarly journals Some Considerations on Tunneling Losses in Field-Effect Devices for Low-Voltage Microcontrollers

1998 ◽  
Vol 21 (1) ◽  
pp. 57-60 ◽  
Author(s):  
M. A. Grado-Caffaro ◽  
M. Grado-Caffaro
Keyword(s):  
Electric Field ◽  
Oxide Layer ◽  
Power Density ◽  
Field Effect ◽  
Low Voltage ◽  
Tunneling Current ◽  
Oxide Thickness ◽  
High Electric Field ◽  
Floating Gate ◽  
Field Effect Devices

The loss power density associated with the tunneling current in a typical MOS cell with a floating gate is evaluated for high electric-field strengths in the oxide layer. Furthermore, problems related to oxide thickness are discussed.

scholarly journals Centeral Electric Field and Threshold Voltage in Accumulation Mode Junctionless Cylindrical Surrounding Gate MOSFET

2018 ◽  
Vol 8 (2) ◽  
pp. 673
Author(s):  
Hakkee Jung
Keyword(s):  
Electric Field ◽  
Threshold Voltage ◽  
Oxide Thickness ◽  
Channel Length ◽  
Accumulation Mode ◽  
Transfer Characteristics ◽  
Threshold Voltages ◽  
Analytical Potential ◽  
Surrounding Gate ◽  
Dimensional Simulation

Transfer characteristics is presented using analytical potential distribution of accumulation-mode junctionless cylindrical surrounding-gate (JLCSG) MOSFET, and deviation of center electric field at threshold voltage is analyzed for channel length and oxide thickness. Threshold voltages presented in this paper is good agreement with results of other compared papers, and transfer characteristics is agreed with those of two-dimensional simulation. The most important factor to determine threshold voltage is center electric field at source because the greater part of electron flows through center axis of JLCSG MOSFET. As a result of analysis for center electric field at threshold voltage, center electric field is decreased with reduction of channel length due to drain induced barrier lowering. Center electric field is increased with decrease of oxide thickness, and deviation of center electric field for channel length is significantly occurred with decrease of oxide thickness.

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