scholarly journals Some Considerations on Tunneling Losses in Field-Effect Devices for Low-Voltage Microcontrollers

1998 ◽  
Vol 21 (1) ◽  
pp. 57-60 ◽  
Author(s):  
M. A. Grado-Caffaro ◽  
M. Grado-Caffaro
Keyword(s):  
Electric Field ◽  
Oxide Layer ◽  
Power Density ◽  
Field Effect ◽  
Low Voltage ◽  
Tunneling Current ◽  
Oxide Thickness ◽  
High Electric Field ◽  
Floating Gate ◽  
Field Effect Devices

The loss power density associated with the tunneling current in a typical MOS cell with a floating gate is evaluated for high electric-field strengths in the oxide layer. Furthermore, problems related to oxide thickness are discussed.

The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  
Keyword(s):  
Electric Field ◽  
Three Dimensional ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Normal Electric Field ◽  
Surface Electric Field ◽  
Tunneling Behavior ◽  
Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

scholarly journals Infrared conductivity of hole accumulation and depletion layers in (Ga,Mn)As- and (Ga,Be)As-based electric field-effect devices

2012 ◽  
Vol 86 (16) ◽  
Author(s):  
B. C. Chapler ◽  
S. Mack ◽  
L. Ju ◽  
T. W. Elson ◽  
B. W. Boudouris ◽  
...  
Keyword(s):  
Electric Field ◽  
Field Effect ◽  
Electric Field Effect ◽  
Field Effect Devices

Optimization of Pt/SBT/CeO2/Si(100) gate stacks for low voltage ferroelectric field effect devices

2001 ◽  
Vol 34 (1-4) ◽  
pp. 47-54 ◽  
Author(s):  
Thomas P. Haneder ◽  
Wolfgang Hönlein ◽  
Harald Bachhofer ◽  
Henning Von Philipsborn ◽  
Rainer Waser
Keyword(s):  
Field Effect ◽  
Low Voltage ◽  
Gate Stacks ◽  
Field Effect Devices

scholarly journals Electric-field effect devices made of YBa2Cu3O7−x/SrTiO3 epitaxial multilayers

1994 ◽  
Vol 224 (1-2) ◽  
pp. 179-184 ◽  
Author(s):  
K. Joosse ◽  
Yu.M. Boguslavskij ◽  
G.J. Gerritsma ◽  
H. Rogalla ◽  
J.G. Wen ◽  
...  
Keyword(s):  
Electric Field ◽  
Field Effect ◽  
Electric Field Effect ◽  
Field Effect Devices ◽  
Epitaxial Multilayers

scholarly journals A Quantitative Analysis of Tunneling Current in A MOS Cell for A Low-Voltage Microcontroller

1998 ◽  
Vol 20 (3) ◽  
pp. 165-167 ◽  
Author(s):  
M. A. Grado-Caffaro ◽  
M. Grado-Caffaro
Keyword(s):  
Quantitative Analysis ◽  
Current Density ◽  
Low Voltage ◽  
Tunneling Current ◽  
Approximate Expression ◽  
Oxide Thickness ◽  
Charge Carriers

The tunneling current density in a MOS cell for a low-voltage microcontroller based on EEPROM is calculated for high electric strengths. Furthermore, this current density is discussed in terms of the oxide thickness and an approximate expression for the velocity of charge carriers is derived.

Performance analysis of junctionless carbon nanotube field effect transistors using NEGF formalism

2016 ◽  
Vol 30 (10) ◽  
pp. 1650125 ◽  
Author(s):  
Saber Barbastegan ◽  
Ali Shahhoseini
Keyword(s):  
Carbon Nanotube ◽  
Field Effect ◽  
Low Voltage ◽  
Field Effect Transistors ◽  
Tunneling Current ◽  
Order Of Magnitude ◽  
Effect Transistor ◽  
Non Equilibrium Green’S Function ◽  
Bias Condition ◽  
Intrinsic Gain

This paper presents the simulation study of a junctionless carbon nanotube field effect transistor (JL-CNTFET) and a comparison is made with the conventional CNTFET using the atomistic scale simulation, within the non-equilibrium Green’s function (NEGF) formalism. In order to have a comprehensive analysis, both analog and digital parameters of the device are studied. Results have shown that JL-CNTFET with respect to C-CNTFET shows slightly higher [Formula: see text] ratio about two times larger than that of C-CNTFET, smaller electric field along channel more than three order of magnitude and reduced tunneling current about 100 times. In addition, the investigation of analog properties of both devices has exhibited that junctionless structure has a transconductance about two times and an intrinsic gain of 15 dB larger than C-CNTFET in same bias condition which makes JL-CNTFET a promising candidate for low voltage analog applications.

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