Strained-SOI (sSOI) technology for high-performance CMOSFETs in 45nm-or-below technology node

2006 ◽  
Author(s):  
Makoto Yoshimi ◽  
Ian Cayrefourcq ◽  
Carlos Mazure
Keyword(s):  
High Performance ◽  
Technology Node

High-performance circuit design for the RET-enabled 65-nm technology node

2004 ◽  
Author(s):  
Lars W. Liebmann ◽  
Arnold E. Barish ◽  
Zachary Baum ◽  
Henry A. Bonges ◽  
Scott J. Bukofsky ◽  
...  
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Technology Node

Marangoni Dryer Integrated High Performance Cleaner for Cu/Low k Post Strip Clean for 45nm Technology Node and Beyond

2007 ◽  
Vol 134 ◽  
pp. 337-340 ◽  
Author(s):  
Jian She Tang ◽  
Wei Lu ◽  
Bo Xi ◽  
Eli Martinez ◽  
Fred Li ◽  
...  
Keyword(s):  
High Performance ◽  
Water Film ◽  
Water Evaporation ◽  
Wafer Surface ◽  
Particle Removal ◽  
Technology Node ◽  
Patterned Wafers ◽  
Process Characterization ◽  
Free Environment ◽  
Low K

To address the water mark issue from hydrophobic film drying, and the stringent particle removal requirements for the 45nm technology node and beyond, we developed a cleaner with an innovative single wafer Marangoni dryer. The single wafer Marangoni dryer design features and process characterization data are presented in this paper. The major results can be summarized as: (1) With the immersion type Marangoni dryer, as the wafer is lifted out of a DIW bath, a stable and uniform meniscus can be easily maintained, making the single-wafer Marangoni dryer ideal for drying hydrophilic, hydrophobic or hydrophobic/hydrophilic mixed patterned wafers; (2) The new Marangoni dryer leaves ~14nm [1] water film on the wafer after drying, therefore any dissolved or suspended materials contained inside the water film, and potentially left on the wafer surface after water evaporation, is less than 14nm in diameter. This feature is critical for the 45nm technology node and beyond because 23nm particle could be killer defects at these nodes [2]; (3) Because of the strong Marangoni flow effect, high aspect ratio features can be completely dried without leaving any water droplets inside the trenches; therefore copper corrosion can be prevented; (4) The Marangoni dryer uses N2 as the carrier gas, so when a wafer is lifted out of the degasified DIW bath through the N2/IPA spray zone, it is thoroughly dried in an oxygen-free environment before exposure to the ambient environment; (5) The Marangoni dryer is free of electrostatic charge and centrifugal force because of the slow (2mm/s~20mm/s) wafer linear lifting speed compared to linear speed at wafer edge during SRD.

scholarly journals Gate-All-Around FETs: Nanowire and Nanosheet Structure

2020 ◽  
Author(s):  
Jun-Sik Yoon ◽  
Jinsu Jeong ◽  
Seunghwan Lee ◽  
Junjong Lee ◽  
Rock-Hyun Baek
Keyword(s):  
Low Power ◽  
High Performance ◽  
The Other ◽  
Short Channel ◽  
Technology Node ◽  
Channel Characteristics ◽  
Other Hand ◽  
Rc Delay

DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications.

A cost effective embedded DRAM integration for high density memory and high performance logic using 0.15 μm technology node and beyond

2000 ◽  
Vol 47 (7) ◽  
pp. 1499-1506 ◽  
Author(s):  
Daewon Ha ◽  
Dongwon Shin ◽  
Gwan-Hyeob Koh ◽  
Jaegu Lee ◽  
Sanghyeon Lee ◽  
...  
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
High Density ◽  
Technology Node
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