Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) ◽

10.1109/iccdcs.2000.869840 ◽

2002 ◽

Cited By ~ 2

Author(s):

M.A. Pavanello ◽

J.A. Martino ◽

D. Flandre

Keyword(s):

Silicon On Insulator ◽

Floating Body ◽

Fully Depleted ◽

Floating Body Effects

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Persistent Floating‐Body Effects in Fully Depleted Silicon‐on‐Insulator Transistors

physica status solidi (a) ◽

10.1002/pssa.201900948 ◽

2020 ◽

Vol 217 (9) ◽

pp. 1900948 ◽

Cited By ~ 1

Author(s):

Hyungjin Park ◽

Jean-Pierre Colinge ◽

Sorin Cristoloveanu ◽

Maryline Bawedin

Keyword(s):

Silicon On Insulator ◽

Floating Body ◽

Fully Depleted ◽

Floating Body Effects

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A physical charge-based model for non-fully depleted SOI MOSFET's and its use in assessing floating-body effects in SOI CMOS circuits

IEEE Transactions on Electron Devices ◽

10.1109/16.372078 ◽

1995 ◽

Vol 42 (4) ◽

pp. 728-737 ◽

Cited By ~ 62

Author(s):

Dongwook Suh ◽

J.G. Fossum

Keyword(s):

Floating Body ◽

Cmos Circuits ◽

Fully Depleted ◽

Floating Body Effects ◽

Soi Cmos

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Investigation of floating body effects in silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistors

Journal of Applied Physics ◽

10.1063/1.349200 ◽

1991 ◽

Vol 70 (7) ◽

pp. 3912-3919 ◽

Cited By ~ 18

Author(s):

T. Ouisse ◽

G. Ghibaudo ◽

J. Brini ◽

S. Cristoloveanu ◽

G. Borel

Keyword(s):

Metal Oxide ◽

Field Effect ◽

Field Effect Transistors ◽

Metal Oxide Semiconductor ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Floating Body ◽

Floating Body Effects

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Physical modeling of beneficial dynamic floating-body effects in non-fully depleted SOI CMOS circuits

Proceedings. IEEE International SOI Conference ◽

10.1109/soi.1994.514238 ◽

2002 ◽

Cited By ~ 1

Author(s):

Dongwook Suh ◽

J.G. Fossum

Keyword(s):

Physical Modeling ◽

Floating Body ◽

Cmos Circuits ◽

Fully Depleted ◽

Floating Body Effects ◽

Soi Cmos

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Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs

Solid-State Electronics ◽

10.1016/j.sse.2003.12.012 ◽

2004 ◽

Vol 48 (6) ◽

pp. 969-978 ◽

Cited By ~ 22

Author(s):

Mansun Chan ◽

Pin Su ◽

Hui Wan ◽

Chung-Hsun Lin ◽

Samuel K.-H. Fung ◽

...

Keyword(s):

Floating Body ◽

Fully Depleted ◽

Floating Body Effects

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Body current scanning: A novel technique for characterizing the floating body effects and parasitic bipolar action in silicon‐on‐insulator metal‐oxide‐semiconductor transistors

Applied Physics Letters ◽

10.1063/1.105279 ◽

1991 ◽

Vol 59 (12) ◽

pp. 1435-1437 ◽

Cited By ~ 5

Author(s):

Patrick S. Liu ◽

G. P. Li

Keyword(s):

Metal Oxide ◽

Metal Oxide Semiconductor ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Floating Body ◽

Novel Technique ◽

Floating Body Effects

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Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

Chinese Physics B ◽

10.1088/1674-1056/25/3/036103 ◽

2016 ◽

Vol 25 (3) ◽

pp. 036103 ◽

Cited By ~ 1

Author(s):

Pengcheng Huang ◽

Shuming Chen ◽

Jianjun Chen

Keyword(s):

Silicon On Insulator ◽

Floating Body ◽

Body Effect ◽

Fully Depleted ◽

Floating Body Effect ◽

Silicon On Insulator Technology

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One Transistor Floating Body RAM Performances on UTBOX Devices Using the BJT Effect

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v7i2.363 ◽

2012 ◽

Vol 7 (2) ◽

pp. 113-120

Author(s):

Luciano M. Almeida ◽

Katia R. A. Sasaki ◽

M. Aoulaiche ◽

Eddy Simoen ◽

Cor Clayes ◽

...

Keyword(s):

Retention Time ◽

Silicon Film ◽

Random Access ◽

Oxide Thickness ◽

Silicon On Insulator ◽

Floating Body ◽

Fully Depleted ◽

Buried Oxide ◽

Drain Bias ◽

Time Decrease

This work aims to analyze through 2D numerical simulations the minimum drain bias for the onset of the parasitic bipolar transistor (BJT) effect (VLatch) of a Ultra-Thin-Buried-Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) transistor used as a Single-Transistor-Dynamic-Random-Access-Memory (1TDRAM) cell at high temperatures. The buried oxide thickness (tBOX) and silicon film thickness (tSi) variation were also taken into account and initial studies of the retention time (RT) and the data degradation have been performed. It was verified that the latch voltage, the sense margin current, the latch time and the retention time decrease as the temperature rises.

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