SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection

2016 ◽  
Author(s):  
Taizhi Liu ◽  
Chang-Chih Chen ◽  
Jiadong Wu ◽  
Linda Milor
Keyword(s):  
Stability Analysis ◽  
Carrier Injection ◽  
Temperature Instability ◽  
Hot Carrier ◽  
Bias Temperature Instability ◽  
Hot Carrier Injection ◽  
Cache Configurations

scholarly journals 3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

2021 ◽  
Author(s):  
Marcs Ng
Keyword(s):  
Integrated Circuits ◽  
Transmission Rate ◽  
Carrier Injection ◽  
Digital Integrated Circuits ◽  
Negative Bias Temperature Instability ◽  
Hot Carrier ◽  
Bias Temperature Instability ◽  
Hot Carrier Injection ◽  
Capacitive Load ◽  
Ac Transmission

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.

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