Vacuum gate dielectric gate-all-around nanowire for hot carrier injection and bias temperature instability free transistor

2014 ◽  
Vol 104 (25) ◽  
pp. 253506 ◽  
Author(s):  
Jin-Woo Han ◽  
Dong-Il Moon ◽  
Jae Sub Oh ◽  
Yang-Kyu Choi ◽  
M. Meyyappan
2021 ◽  
Author(s):  
Marcs Ng

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.


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