Reliability Evaluation of Copper (Cu) Through-Silicon Vias (TSV) Barrier and Dielectric Liner by Electrical Characterization and Physical Failure Analysis (PFA)

2017 ◽  
Author(s):  
Jiawei Marvin Chan ◽  
Xu Cheng ◽  
Kheng Chooi Lee ◽  
Werner Kanert ◽  
Chuan Seng Tan
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Reliability Evaluation ◽  
Through Silicon Vias ◽  
Silicon Vias

Failure and Stress Analysis of Cu TSVs Using GHz-Scanning Acoustic Microscopy and Scanning Infrared Polariscopy

2015 ◽  
Author(s):  
Ingrid De Wolf ◽  
Ahmad Khaled ◽  
Martin Herms ◽  
Matthias Wagner ◽  
Tatjana Djuric ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Stress Analysis ◽  
Rayleigh Waves ◽  
Acoustic Microscopy ◽  
Scanning Acoustic Microscopy ◽  
Through Silicon Vias ◽  
Stress Anisotropy ◽  
Silicon Vias ◽  
Ic Technology ◽  
Detection Of Defects

Abstract This paper discusses the application of two different techniques for failure analysis of Cu through-silicon vias (TSVs), used in 3D stacked-IC technology. The first technique is GHz Scanning Acoustic Microscopy (GHz- SAM), which not only allows detection of defects like voids, cracks and delamination, but also the visualization of Rayleigh waves. GHz-SAM can provide information on voids, delamination and possibly stress near the TSVs. The second is a reflection-based photoelastic technique (SIREX), which is shown to be very sensitive to stress anisotropy in the Si near TSVs and as such also to any defect affecting this stress, such as delamination and large voids.

Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias

2012 ◽  
Vol 22 (5) ◽  
pp. 055021 ◽  
Author(s):  
Pradeep Dixit ◽  
Tapani Vehmas ◽  
Sami Vähänen ◽  
Philippe Monnoyer ◽  
Kimmo Henttinen
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
Electrical Characterization ◽  
Through Silicon Vias ◽  
Poly Silicon ◽  
Silicon Vias

Characterization and Failure Analysis of Wafer Bonded Devices and Unfilled Through-Silicon-Vias (TSVs)

2008 ◽  
Author(s):  
C. Cassidy ◽  
J. Kraft ◽  
G. Koppitsch ◽  
E. Brandlhofer ◽  
M. Steiner ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Semiconductor Devices ◽  
3D Integration ◽  
Through Silicon Vias ◽  
Silicon Vias

Abstract This paper is concerned with characterization and failure analysis challenges posed by 3D integration of semiconductor devices, with a particular focus on wafer bonded components and Through Silicon Vias (TSV). Requirements for sample preparation are discussed, along with advantages and limitations exhibited by various different techniques. Analysis examples with real devices are presented, along with successful sample preparation solutions enabled by a precision polishing toolset.

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