Die Bonding with Non-Clean Flux in Fine Pitch Copper Pillar Bump Study and Reliability Performance for 2.5D IC Package

2016 ◽  
Author(s):  
J. C. Liao ◽  
Ally Liao ◽  
Sam Peng ◽  
G. T. Lin ◽  
Terrence Lu ◽  
...  
Keyword(s):  
Fine Pitch ◽  
Die Bonding ◽  
Reliability Performance ◽  
Ic Package

Die to Die and Die To Wafer Bonding Solution for High Density, Fine Pitch Micro-Bumped Die

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002251-002284 ◽  
Author(s):  
Gilbert Lecarpentier ◽  
Joeri De Vos
Keyword(s):  
Wafer Bonding ◽  
Flip Chip ◽  
High Accuracy ◽  
High Density ◽  
Size Reduction ◽  
Direct Impact ◽  
3 Dimensional ◽  
Fine Pitch ◽  
Placement Accuracy ◽  
Die Bonding

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch

Process Feasibility and Reliability Performance of Fine Pitch Si Bare Chip Embedded in Through Cavity of Substrate Core

2015 ◽  
Vol 5 (4) ◽  
pp. 551-561 ◽  
Author(s):  
Younggun Han ◽  
Osamu Horiuchi ◽  
Shigehiro Hayashi ◽  
Kanta Nogita ◽  
Yoshihisa Katoh ◽  
...  
Keyword(s):  
Fine Pitch ◽  
Reliability Performance

Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001870-001893
Author(s):  
Rajesh Katkar ◽  
Zhijun Zhao ◽  
Ron Zhang ◽  
Rey Co ◽  
Laura Mirkarimi
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Temperature Cycling ◽  
Memory Bandwidth ◽  
Free Standing ◽  
Element Analysis ◽  
Fine Pitch ◽  
Solder Balls ◽  
High Bandwidth ◽  
Reliability Performance

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

scholarly journals Technical Barriers and Development of Cu Wirebonding in Nanoelectronics Device Packaging

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
C. L. Gan ◽  
E. K. Ng ◽  
B. L. Chan ◽  
U. Hashim ◽  
F. C. Classe
Keyword(s):  
Success Factors ◽  
Bonding Parameters ◽  
Green Mold ◽  
Fine Pitch ◽  
Bga Package ◽  
Bond Interface ◽  
Ball Bonds ◽  
Cu Bonding ◽  
Reliability Performance ◽  
Intermetal Dielectric

Bondpad cratering, Cu ball bond interface corrosion, IMD (intermetal dielectric) cracking, and uncontrolled post-wirebond staging are the key technical barriers in Cu wire development. This paper discusses the UHAST (unbiased HAST) reliability performance of Cu wire used in fine-pitch BGA package. In-depth failure analysis has been carried out to identify the failure mechanism under various assembly conditions. Obviously green mold compound, low-halogen substrate, optimized Cu bonding parameters, assembly staging time after wirebonding, and anneal baking after wirebonding are key success factors for Cu wire development in nanoelectronic packaging. Failure mechanisms of Cu ball bonds after UHAST test and CuAl IMC failure characteristics have been proposed and discussed in this paper.

Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001432-001451
Author(s):  
Anupam Choubey ◽  
E. Anzures ◽  
A. Dhoble ◽  
D. Fleming ◽  
M. Gallagher ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Fatigue Testing ◽  
Electrical Performance ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
Semiconductor Packages ◽  
Reliability Performance ◽  
3D Chip Stacking

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Techniques in Extracting CSP Device from Underfilled PCB Module and Performing Solder Rework and Reballing for ATE Testing

2017 ◽  
Author(s):  
Kah Chin Cheong
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Printed Circuit Board ◽  
Semiconductor Industry ◽  
Mechanical Damage ◽  
Circuit Board ◽  
Fine Pitch ◽  
Chip Scale Package ◽  
Reliability Performance ◽  
Capillary Underfill

Abstract The application of underfill materials for board level assembly has been increasing rapidly in semiconductor industry to enhance strength and reliability performance of semiconductor components in harsh environments. However, due to the intractability of the capillary underfill after curing, extracting a chip scale package (CSP) device from a printed circuit board (PCB) with a combination of mold compound and capillary underfill for ATE testing has become difficult and challenging. This poses a severe limitation to this technology regarding electrical testing and failure analysis. In order to address the challenge in extracting a CSP device from an underfilled PCB without inducing any mechanical damage, a series of sample preparation techniques has been introduced. This paper discusses the techniques in removing the fine pitch CSP device from underfilled PCB module in a relatively simple way which includes application of chemical solutions, de-soldering, residual solder remnants cleaning and reballing. The established process enables ATE testing, electrical testing and failure analysis to be performed on any CSP devices. An electrical evaluation on the efficiency of a CSP device after a series of sample preparation processes will also be highlighted.

scholarly journals Wearout Reliability and Intermetallic Compound Diffusion Kinetics of Au and PdCu Wires Used in Nanoscale Device Packaging

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
C. L. Gan ◽  
E. K. Ng ◽  
B. L. Chan ◽  
F. C. Classe ◽  
T. Kwuanjai ◽  
...  
Keyword(s):  
Intermetallic Compound ◽  
Semiconductor Device ◽  
Technical Information ◽  
Diffusion Kinetics ◽  
Nanoscale Device ◽  
Bga Packages ◽  
Fine Pitch ◽  
Ball Bonds ◽  
Reliability Performance ◽  
Kinetics Of

Wearout reliability and diffusion kinetics of Au and Pd-coated Cu (PdCu) ball bonds are useful technical information for Cu wire deployment in nanoscale semiconductor device packaging. This paper discusses the HAST (with bias) and UHAST (unbiased HAST) wearout reliability performance of Au and PdCu wires used in fine pitch BGA packages. In-depth failure analysis has been carried out to identify the failure mechanism under various wearout conditions. Intermetallic compound (IMC) diffusion constants and apparent activation energies (Eaa) of both wire types were investigated after high temperature storage life test (HTSL). Au bonds were identified to have faster IMC formation, compared to slower IMC growth of PdCu. PdCu wire was found to exhibit equivalent or better wearout reliability margin compared to conventional Au wire bonds. Failure mechanisms of Au, Cu ball bonds post-HAST and UHAST tests are been proposed, and both Au and PdCu IMC diffusion kinetics and their characteristics are discussed in this paper.

scholarly journals Reliability Assessment and Activation Energy Study of Au and Pd-Coated Cu Wires Post High Temperature Aging in Nanoscale Semiconductor Packaging

2013 ◽  
Vol 135 (2) ◽  
Author(s):  
C. L. Gan ◽  
U. Hashim
Keyword(s):  
Activation Energy ◽  
High Temperature ◽  
Semiconductor Device ◽  
Formation Rate ◽  
Technical Information ◽  
Ball Bond ◽  
Fine Pitch ◽  
Bga Package ◽  
Ball Bonds ◽  
Reliability Performance

Wearout reliability and high temperature storage life (HTSL) activation energy of Au and Pd-coated Cu (PdCu) ball bonds are useful technical information for Cu wire deployment in nanoscale semiconductor device packaging. This paper discusses the influence of wire type on the wearout reliability performance of Au and PdCu wire used in fine pitch BGA package after HTSL stress at various aging temperatures. Failure analysis has been conducted to identify the failure mechanism after HTSL wearout conditions for Au and PdCu ball bonds. Apparent activation energies (Eaa) of both wire types are investigated after HTSL test at 150 °C, 175 °C and 200 °C aging temperatures. Arrhenius plot has been plotted for each ball bond types and the calculated Eaa of PdCu ball bond is 0.85 eV and 1.10 eV for Au ball bond in 110 nm semiconductor device. Obviously Au ball bond is identified with faster IMC formation rate with IMC Kirkendall voiding while PdCu wire exhibits equivalent wearout and or better wearout reliability margin compare to conventional Au wirebond. Lognormal plots have been established and its mean to failure (t50) have been discussed in this paper.

Finite Element Parametric Analysis on Fine-Pitch BGA (FBGA) Packages

2003 ◽  
Author(s):  
Desmond Y. R. Chong ◽  
C. K. Wang ◽  
K. C. Fong ◽  
Pradeep Lall
Keyword(s):  
Finite Element ◽  
Integrated Circuit ◽  
Parametric Analysis ◽  
Substrate Thickness ◽  
Cellular Phones ◽  
Fine Pitch ◽  
Board Surface ◽  
Die Stress ◽  
Ic Package ◽  
Surface Mounting

Reduction in size of portable products such as cellular phones and camcorders has led to the miniaturization of integrated circuit packages. Fine-pitch BGA (FBGA) packages has been gaining its popularity due to compact in size and relatively low costing. With further down-sizing in package height, reliability issues like die cracking and warpage have surfaced as potential failures. Die cracks results in malfunction of an IC package, while the latter causes difficulty in board surface mounting. In this study, effects of package height on the die stress and warpage have been assessed by FEA. With overmold height ranging from 0.4∼0.6mm and substrate from 0.16∼0.32mm thick, the Overall Package Thickness coding from “T” (1.00<A< = 1.20mm) to “W” (0.65<A< = 0.80mm) are being analyzed. Results revealed that die stress and warpage decreases with increase in overmold thickness. However, an increment in the substrate thickness constituted to a rise in die stress and warpage. It was found that “top clearance” (distance between active die side and package top) of the package contributed to different trends in die stresses. Trends of results in varying the package and die sizes are also being investigated. The findings have provided guidelines for in-house designers in containing possible failures in FBGA packages.

Chip-last Embedded Actives and Passives in Ultra-Miniaturized Organic Packages with Chip-First Benefits

2010 ◽  
Vol 2010 (1) ◽  
pp. 000537-000542
Author(s):  
Nitesh Kumbhat ◽  
Fuhan Liu ◽  
Venky Sundaram ◽  
Vivek Sridharan ◽  
Abhishek Choudhury ◽  
...  
Keyword(s):  
High Performance ◽  
Metal Layer ◽  
Stress Test ◽  
Heterogeneous Systems ◽  
Wafer Level ◽  
Fine Pitch ◽  
Low Profile ◽  
Organic Packages ◽  
Accelerated Stress Test ◽  
Reliability Performance

Embedded actives and passives are being pursued by chip-first and wafer-level fan-out approaches to address high functionality and miniaturization. A next generation embedding alternative- “chip-last embedding”, which retains all the benefits of chip-first, has been demonstrated at Georgia Tech for complex multi-component heterogeneous systems. This paper presents detailed results from the first demonstration of this novel technology called Embedded MEMS, Actives and Passives (EMAP) with Chip-Last (CL) interconnections. This technology is targeted at highly integrated modules and systems with multiple 2D and 3D ICs for RF, Digital, Analog, MEMS and passive devices. Ultra-thin (55μm) silicon test dies were embedded in a 60μm deep cavity within 6-metal layer substrates yielding a total module thickness of 0.22mm. The robustness of substrate materials and processes was demonstrated using thermal cycling of the blind-vias and through-holes. The embedded IC was bonded to the substrate at 160°C by ultra-fine pitch (30–50μm) and low-profile (10–15μm) Cu-to-Cu interconnections with polymer adhesives. Two different die-sizes 3mm × 3mm and 7mm × 7mm were investigated for reliability performance of these interconnections, which passed 1000 thermal cycles, in addition to Highly Accelerated Stress Test (HAST) and High Temperature Storage Test (HTS). Comprehensive analysis of new materials and processes used in the chip-last embedding technology has been carried out demonstrating the advantages and robustness of this promising technology. Due to manufacturing process simplicity and unparalleled set of benefits, the chip-last technology provides the benefits of chip-first while enabling highly miniaturized, multi-band, high performance modules with embedded actives and passives.

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