Ultra-fine pitch Package on Package solution for high bandwidth mobile applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001870-001893
Author(s):  
Rajesh Katkar ◽  
Zhijun Zhao ◽  
Ron Zhang ◽  
Rey Co ◽  
Laura Mirkarimi
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Temperature Cycling ◽  
Memory Bandwidth ◽  
Free Standing ◽  
Element Analysis ◽  
Fine Pitch ◽  
Solder Balls ◽  
High Bandwidth ◽  
Reliability Performance

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.

A Slim Sector Model for the Analysis of Fatigue Life of Fine Pitch Flip Chip Packages

2005 ◽  
Author(s):  
Bing Zhao ◽  
Andrew A. O. Tay
Keyword(s):  
Fatigue Life ◽  
Flip Chip ◽  
Computation Time ◽  
Critical Issue ◽  
Temperature Cycling ◽  
Element Analysis ◽  
Sector Model ◽  
Fine Pitch ◽  
Time Required ◽  
Diagonal Plane

In the near future, it is likely that the interconnection pitch of flip chips will fall below 100 microns. For a flip chip of 20mm × 20mm at this pitch, there will be 40,000 interconnections on the chip. Even after taking advantage of symmetry whereby only a one-eighth model need be analyzed, there will be 5,000 interconnections. If solder were used to form the interconnection, plasticity and creep effects would need to be taken into account. Despite the great advances in computer technology, the computer memory and computation time required for a full 3D finite element analysis (FEA) of such a fine-pitch IC package is prohibitive. This paper presents a slim sector model which could be used to overcome this problem. Essentially, a slim sector of the package adjacent to the diagonal is analyzed rather than a 1/8 model. The appropriate boundary condition to be applied to the slim sector model is a critical issue. With the large number of interconnections, it is reasonable to expect that the displacement of points close to the diagonal plane of the package will tend to be directed radially outwards from the neutral point at the centre of the package. The validity of this assumption was investigated by performing a full 3D FEA of the 1/8 model of two flip chip packages of dimensions 4mm square and 6mm square. A few slim sector models have been developed and their accuracy and computational efficiency studied. The fatigue life of the critical solder joint was determined by performing a temperature cycling simulation between −40C and 150C. The elastoplastic and creep properties of solder were taken into account. As the 1/8 model is the most accurate model, its results were taken as reference. It was found that the accuracy of the best slim sector model ranged between 12% and 27%. A comparison was also made between the slim sector model and the popular strip model. It was found that the slim sector model was much more accurate than the strip model which gives error of 61–248%.

Fine Pitch Copper Interconnects for Next Generation Package-on-Package (PoP)

2012 ◽  
Vol 2012 (1) ◽  
pp. 001137-001142 ◽  
Author(s):  
Ilyas Mohammed
Keyword(s):  
High Performance ◽  
Copper Interconnects ◽  
Free Standing ◽  
Positional Accuracy ◽  
Aspect Ratios ◽  
Fine Pitch ◽  
Wire Bonds ◽  
Solder Balls ◽  
The Wire ◽  
Interconnect Technology

For low power processors, stacking memory on top offers many advantages such as high performance due to memory-processor interface within package, small footprint and standard assembly. Package-on-package (PoP) is preferred method of stacking as it offers two discrete packages that are tested separately and can be sourced independently. However, current PoP interconnect technologies do not efficiently scale to meet the memory bandwidth requirements for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap, or using organic interposers are not practically achieving the high IO requirements, since the aspect ratios of these interconnects are limited. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology called Bond Via Array (BVA™) is presented that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. The three main challenges were forming free standing wire-bonds, molding the package while exposing the tips of the wire-bonds, and package stacking. The assembly results showed that the wire tips were within the desired positional accuracy and height, and the packages were stacked without any loss of yield. These results indicate that the BVA interconnect technology is promising for the very high density and fine pitch required for upcoming mobile computing systems.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

Fabrication and Reliability Assessment of Cu Pillar Micro-bumps with Printed Polymer Cores

2020 ◽  
Author(s):  
Xing QIU ◽  
Jeffery Lo ◽  
Yuanjie CHENG ◽  
Shi-Wei Ricky Lee ◽  
Yong Jhe TSENG ◽  
...  
Keyword(s):  
Flip Chip ◽  
Reliability Assessment ◽  
Temperature Cycling ◽  
Thermomechanical Stress ◽  
Joint Reliability ◽  
Cu Pillar ◽  
Bonding Technology ◽  
Temperature Cycling Test ◽  
Reliability Performance ◽  
Cycling Condition

Abstract Cu pillar micro-bumps with polymer cores have been demonstrated to effectively reduce thermomechanical stress and improve joint reliability. Fabricating polymer cores by a printing approach was proposed to overcome the limitations in conventional fabrication process. Cylindrical polymer cores with diameter of 20 µm and height of 30 µm were successfully printed. Surface metallization was subsequently applied on the printed polymer cores and Cu pillar micro-bumps with printed polymer cores with diameter of 35 µm and height of 35 µm were eventually achieved. To study the reliability performance of the interconnect joints made of Cu pillar micro-bumps with printed polymer cores, flip-chip bonding technology was successfully introduced and the interconnect joints between a designed BT substrate and a silicon chip were formed. The interconnect joints made of conventional Cu pillars with identical dimensions were prepared for comparison. The reliability performance of the joints was investigated under temperature cycling condition and drop condition, respectively. Printed polymer cores increased the characteristic life by 32% in a temperature cycling test (0°C-100°C), while the drop test showed that printed polymer cores increased the characteristic life by 4 times due to the extra compliance provided by the printed polymer cores. It can be concluded that Cu pillar micro-bumps with printed polymer cores can effectively reduce stress and improve joint reliability.

Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000930-000959
Author(s):  
Wael Zohni ◽  
Rajesh Katkar ◽  
Rey Co ◽  
Rizza Cizek
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
High Volume ◽  
Third Party ◽  
High Yield ◽  
Test Vehicle ◽  
Industry Standard ◽  
Fine Pitch ◽  
High Bandwidth ◽  
Manufacturing Readiness

Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (>100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years. A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP. This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware. In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.

Advanced Substrate Applied Fluxing Underfill for Bonding of Fine Pitch Solder Capped Cu Pillars to Oxidized Cu Substrates

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000924-000943
Author(s):  
Russell Stapleton ◽  
Jim Greig
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Low Cost ◽  
Cost Effective ◽  
Filler Loading ◽  
Thermal Compression ◽  
Transparent Substrate ◽  
Fine Pitch ◽  
Before And After ◽  
Cu Substrates

Underfill solutions for fine pitch flip chip assemblies is an active area of development. Non-conductive films (NCF) and pastes (NCP) have shown great potential in bridging the gap between no-flow and capillary underfills for improving the reliability of fine pitched devices. But NCFs and NCPs require costly passivated pad finishes (e.g. Au, Sn, Ni, OSP) or careful substrate handling for proper solder joint formation. In this paper, we will describe a new class of underfill material that benefits from the growing trend of using thermal compression bonding as a cost effective alternative to mass reflow based underfilling processes (e.g. capillary and no-flow). This material is a fluxing NCP that is useful for a wide variety of fine pitch substrates, including low cost Cu. The material we will demonstrate contains many advanced features: high filler loading, strong flux activity, long work life, off-tool pre-dispense, low stress, high Tg, high modulus and rapid cure. The all-in-one underfill demonstrated in this paper is applied by using a screen printing process, where the material is applied to all of the chip sites in one step achieving excellent application efficiency and wetting/conformity to the substrate. The substrate is glass, containing a 4x4 array of die sites. Each of the die sites are 5x5mm in size with a full area array of 2501 Cu pads (50um pads on 100um pitch) that are pre-oxidized for 1h at 175C in air prior to printing (to simulate a dehydration bake). This transparent substrate was chosen to show the robust nature of the underfill for fluxing, stability and void-free placement/cure. Images of the substrate, before and after chip bonding will be given, along with cross sections. Details of the material properties will also be discussed.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

2011 ◽  
Vol 2011 (1) ◽  
pp. 000953-000960 ◽  
Author(s):  
Thomas Oppert ◽  
Rainer Dohle ◽  
Jörg Franke ◽  
Stefan Härter
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Solder Paste ◽  
Wafer Level ◽  
Solder Alloys ◽  
Flip Chips ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Cost Efficient

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

Creep Behavior of a Flip-Chip Package by Both FEM Modeling and Real Time Moire´ Interferometry

1998 ◽  
Vol 120 (2) ◽  
pp. 179-185 ◽  
Author(s):  
J. Wang ◽  
Z. Qian ◽  
D. Zou ◽  
S. Liu
Keyword(s):  
Finite Element ◽  
Creep Behavior ◽  
Thermal Load ◽  
Flip Chip ◽  
Moiré Interferometry ◽  
Moire Interferometry ◽  
Initial State ◽  
Element Analysis ◽  
The Finite Element Analysis ◽  
Solder Balls

In this paper, the creep behavior of a flip-chip package under a thermal load was investigated by using nonlinear finite element technique coupled with high density laser moire´ interferometry. The real-time moire´ interferometry technique was used to monitor and measure the time-dependent deformation of flip-chip packages during the test, while the finite element method was adapted to analyze the variation of stresses at edges and corners of interfaces with time by considering the viscoelastic properties of the underfill and the viscoplastic behavior of the solder balls. The results show that the creep behavior of the underfill and the solder balls does not have significant effect on the warpage of the flip-chip under the considered thermal load due to their constrained small volume. The variation of the time-dependent deformation in the flip-chip package caused by the creep behavior of the underfill and the solder balls is in the submicro scale. The maximum steady-state U-displacement is only reduced by up to 6.7 percent compared with the maximum initial state U-displacement. Likewise, the maximum steady-state V-displacement is merely reduced by up to 10 percent compared with the maximum initial state V-displacement. The creep behavior slightly weakens the warpage situation of the flip-chip package. However, the modeling results show that the localized stresses at corners and edges of interfaces greatly decrease due to the consideration of viscoelastic properties of the underfill and the viscoplastic properties of the solder balls, and, thereby, effectively preventing interfaces from cracking. In addition, the predicted deformation values of the flip-chip package obtained from the finite element analysis were compared with the test data obtained from the laser moire´ interferometry technique. It is shown that the deformation values of the flip-chip package predicted from the finite element analysis are in a fair agreement with those obtained from the test.

High Reliability Underfill for Flip-Chip Application

1996 ◽  
Vol 445 ◽  
Author(s):  
K. Sumita ◽  
K. Kumagae ◽  
K. Dobashi ◽  
T. Shiobara ◽  
M. Kuroda
Keyword(s):  
Ring Opening ◽  
Flip Chip ◽  
High Reliability ◽  
Void Formation ◽  
Ring Opening Polymerization ◽  
Organic Substrate ◽  
Temperature Cycling ◽  
Excellent Adhesion ◽  
Reliability Performance ◽  
Modified Epoxy

AbstractA new underfill was developed for a flip chip application with a large VLSI die. The new underfill is resistant to hydrolysis, exhibits a significantly lower moisture saturation level than widely used carboxylic anhydride cured underfills, demonstrates superb penetration capability between such a large die and an organic substrate without void formation, and delivers excellent adhesion characteristics and reliability performance during temperature cycling test and PCT (pressure cooker test).The new underfill utilizes amine catalyzed ring opening polymerization of epoxides, forms ether linkages during cure rather than ester linkages which anhydride cured underfills form, and strongly resists to hydrolysis. The underfill is less sensitive to moisture contamination and provides improved floor life as well as storage life in contrast to anhydride cured underfills as well. Unique low stress performance and penetration capability of the underfill are attributed to the use of proprietary silicone modified epoxy resin as well as highly loaded filler of optimized size, shape and size distribution in reference to the gap between a die and an organic substrate.An optimum cure schedule and a desirable viscosity range have also been identified for the new underfill to minimize filler segregation. Proper preheating of a die‐substrate has effectively reduced void formation while facilitating the removal of volatile from an organic substrate.

Sign in / Sign up

Export Citation Format

Share Document