Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS-NEM Hybrid Circuits

Considering the isotropic release process of nanoelectromechanical systems (NEMS), defining the active region of NEM memory switches is one of the most challenging process technologies for the implementation of monolithic-three-dimensional (M3D) CMOS-NEM hybrid circuits. In this paper, we propose a novel encapsulation method of NEM memory switches. It uses alumina (Al2O3) passivation layers which are fully compatible with CMOS baseline process. The Al2O3 bottom passivation layer can protect intermetal dielectric (IMD) and metal interconnection layers from vapor hydrogen fluoride (HF) etch process. Thus, the controllable formation of the cavity for the mechanical movement of NEM memory switches can be achieved without causing any damage to CMOS baseline circuits as well as metal interconnection lines. As a result, NEM memory switches can be located in any places and metal layers of an M3D CMOS-NEM hybrid chip, which makes circuit design easier and more volume-efficient. The feasibility of our proposed method is verified based on experimental results.

Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS-NEM Hybrid Circuits

Considering the isotropic release process of nanoelectromechanical systems (NEMS), defining the active region of NEM memory switches is one of the most challenging process technologies for the implementation of monolithic-three-dimensional (M3D) CMOS-NEM hybrid circuits. In this paper, we propose a novel encapsulation method of NEM memory switches. It uses alumina (Al2O3) passivation layers which are fully compatible with CMOS baseline process. The Al2O3 bottom passivation layer can protect intermetal dielectric (IMD) and metal interconnection layers from vapor hydrogen fluoride (HF) etch process. Thus, the controllable formation of the cavity for the mechanical movement of NEM memory switches can be achieved without causing any damage to CMOS baseline circuits as well as metal interconnection lines. As a result, NEM memory switches can be located in any places and metal layers of an M3D CMOS-NEM hybrid chip, which makes circuit design easier and more volume-efficient. The feasibility of our proposed method is verified based on experimental results.

Oxide Impurities in Silicon Oxide Intermetal Dielectrics and Their Potential to Elevate Via-Resistances

Silicon oxide used as an intermetal dielectric (IMD) incorporates oxide impurities during both its formation and subsequent processing to create vias in the IMD. Without a sufficient degassing of the IMD, oxide impurities released from the IMD during the physical vapor deposition (PVD) of the glue layer of the vias had led to an oxidation of the glue layer and eventual increase of the via resistances, which correlated with the O-to-Si atomic ratio of the IMD being ~10% excessive as verified by transmission electron microscopy (TEM) analysis. A vacuum bake of the IMD was subsequently implemented to enhance outgassing of the oxide impurities in the IMD before the glue layer deposition. The implementation successfully reduced the via resistances to an acceptable level.

High-k dielectrics for hybrid floating gate memory applications

ABSTRACTWe report on the materials issues involved in the hybrid floating gate (HFG) device fabrication, where the interpoly dielectric is replaced by an intermetal dielectric (IMD). Indeed, in HFG the dielectric is inserted in between two metal layers in a metal\dielectric\metal stack. The materials of choice were TiN as the metal layer and Al2O3 and HfO2 (and their combination) as IMD. The program/erase performance is discussed based on the dielectric constant and crystallinity of the IMD and the metal-IMD interface characteristics.

Technical Barriers and Development of Cu Wirebonding in Nanoelectronics Device Packaging

Bondpad cratering, Cu ball bond interface corrosion, IMD (intermetal dielectric) cracking, and uncontrolled post-wirebond staging are the key technical barriers in Cu wire development. This paper discusses the UHAST (unbiased HAST) reliability performance of Cu wire used in fine-pitch BGA package. In-depth failure analysis has been carried out to identify the failure mechanism under various assembly conditions. Obviously green mold compound, low-halogen substrate, optimized Cu bonding parameters, assembly staging time after wirebonding, and anneal baking after wirebonding are key success factors for Cu wire development in nanoelectronic packaging. Failure mechanisms of Cu ball bonds after UHAST test and CuAl IMC failure characteristics have been proposed and discussed in this paper.