Analysis on Signal and Power Integrity of 2.3D Structure Organic Package

Heterogeneous packaging is one of the advanced technologies. Especially for high-end applications such as data center server, HPC and Artificial-Intelligence (AI), High-Bandwidth Memory (HBM) integration is a key and strongly required. As we know, the 2.5D silicon interposer packaging is an expanded solution for HBM interconnections. However, we developed 2.1D high density organic package called i-THOP® (integrated-Thin film High density Organic Package) to take advantages of an organic solution. Furthermore, we are now focusing on 2.3D i-THOP® to have more benefits in the manufacturing. The 2.3D structure consists of two substrates. One is a thin i-THOP® interposer, the other one is a conventional build-up (BU) substrate. These two substrates are combined as the interposer placed onto the build-up substrate. In this paper, the electrical properties of 2.3D i-THOP® are studied to confirm the possibility of the 2.3D structure organic packages from the perspective of signal and power integrity. Firstly, the signal integrity between two devices is simulated, comparing the differences between i-THOP® and the 2.5D silicon interposer. Secondly, the signal integrity in die-to-substrate vertical interconnection is simulated, comparing between 2.1D, 2.3D i-THOP® and the 2.5D silicon interposer. Finally, as for the power delivery point of view, power distribution network (PDN) impedance is compared between 2.1D and 2.3D i-THOP®.

Thermal and Reliability Demonstration of a Large Die on a Low CTE Chip Scale Package

In organic packages, large die and large laminate body sizes are susceptible to CTE (coefficient of thermal expansion) mismatch driven warpage, stresses and strains, which can result in C4 white bumps, micro Ball Grid Array (BGA) interconnection issues, and package thermal reliability concerns. Low CTE carriers minimize these concerns and allow increased chip join yields and improved package reliability. Modeling and characterization of warpage, chip and micro BGA integrity and electrical characterization of a low CTE, Chip Scale Package (CSP) were described in an earlier paper. In this paper we report the progress on the next phase - thermal and chip package interaction (CPI) evaluation of a single chip CSP designed for use with Multi-Chip Modules (MCM). Assembly, characterization, thermal performance and reliability stress results of these low CTE CSP Single Chip Modules (SCMs) are described. Measured warpage values are compared with thermo-mechanical modeling results. Demonstration of a dual CSP design and assembly with large dies is also presented. The successful demonstration of the material set, bond and assembly processes, and reliability of a large die, high I/O CSP, followed by the demonstration of a dual CSP on a multi component carrier, are fore-runners to the development of multi-CSP MCMs.