Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package

2009 ◽  
Author(s):  
Xiaowu Zhang ◽  
T.C. Chai ◽  
John H. Lau ◽  
C. S. Selvanayagam ◽  
Kalyan Biswas ◽  
...  
Keyword(s):  
Through Silicon Via ◽  
Fine Pitch ◽  
Low K

Assembly of large dies fine pitch Cu/low-k FCBGA package with through silicon via (TSV) interposer

2009 ◽  
Author(s):  
Leong Ching Wai ◽  
Xiaowu Zhang ◽  
T C Chai ◽  
Vempati Rao Srinivas ◽  
David Ho ◽  
...  
Keyword(s):  
Through Silicon Via ◽  
Fine Pitch ◽  
Low K

Development of Large Die Fine-Pitch Cu/Low-$k$ FCBGA Package With Through Silicon via (TSV) Interposer

2011 ◽  
Vol 1 (5) ◽  
pp. 660-672 ◽  
Author(s):  
Tai Chong Chai ◽  
Xiaowu Zhang ◽  
J H Lau ◽  
C S Selvanayagam ◽  
P Damaruganath ◽  
...  
Keyword(s):  
Through Silicon Via ◽  
Fine Pitch ◽  
Low K

Fine‐pitch through‐silicon via integration with self‐aligned back‐side benzocyclobutene passivation layer

2016 ◽  
Vol 11 (10) ◽  
pp. 619-622 ◽  
Author(s):  
Yong Guan ◽  
Shenglin Ma ◽  
Qinghua Zeng ◽  
Jing Chen ◽  
Yufeng Jin
Keyword(s):  
Passivation Layer ◽  
Back Side ◽  
Through Silicon Via ◽  
Fine Pitch

Development of a Cu/Low-$k$ Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications

2011 ◽  
Vol 1 (3) ◽  
pp. 299-309 ◽  
Author(s):  
Xiaowu Zhang ◽  
J H Lau ◽  
C S Premachandran ◽  
Ser-Choong Chong ◽  
Leong Ching Wai ◽  
...  
Keyword(s):  
Ball Grid Array ◽  
Fine Pitch ◽  
Low K

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

2011 ◽  
Vol 2011 (1) ◽  
pp. 000828-000836
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Aging Process ◽  
Flip Chip ◽  
Fem Simulation ◽  
Organic Substrate ◽  
Organic Substrates ◽  
Cross Sectional ◽  
Pillar Height ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Low K

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

Si Vapor Chamber Integrated with Through Silicon Via for 3D Packaging

2013 ◽  
Vol 2013 (1) ◽  
pp. 000552-000557 ◽  
Author(s):  
Jun Taniguchi ◽  
Takeshi Shioga ◽  
Yoshihiro Mizuno
Keyword(s):  
Thermal Resistance ◽  
Heat Dissipation ◽  
Working Fluid ◽  
In Situ Observation ◽  
Vapor Chamber ◽  
Cover Glass ◽  
Through Silicon Via ◽  
Improvement Rate ◽  
Fine Pitch ◽  
3D Packaging

We demonstrate an etched silicon vapor chamber integrated with a through-silicon via (TSV) for 3D packaging. The Si vapor chamber chip enables low mismatch in the thermal expansion coefficient of a Si-LSI chip and provides a new heat dissipation path for 3D-LSI inter layer cooling. For the first prototype of the vapor chamber, an outside 33-mm × 33-mm chip consisting of a 25-mm × 25-mm area for the vapor chamber, a wick structure 30-μm high, and a vapor passage 100-μm high is developed. In-situ observation of the behavior of the working fluid through the cover glass and heat transfer enhancement is successfully demonstrated. The improvement rate of thermal resistance is 7.1% compared to a test chip without working fluid. Next, the fluid flow of a second vapor chamber prototype consisting of the first prototype integrated with a TSV structure using a Si pillar of 150-μm diameter is investigated. Thermal resistance and droplet observation conducted to evaluate the influence of the TSV. The operation of the vapor chamber is confirmed when a Si pillar is arranged to a coarse pitch of more than 500 μm. A droplet is generated and the vapor passage is partially obstructed. However, the droplet eventually degenerated and the performance of the vapor chamber is maintained. When the Si pillar is arranged to a fine pitch of 200 μm, the entire vapor passage is blocked during the liquid charging process, and no improvement is observed in the thermal resistance of the chip.

scholarly journals Fine Pitch Wirebonds on Ultra Low-k Device

2011 ◽  
Vol 4 (1) ◽  
pp. 17-23 ◽  
Author(s):  
Takashi Hisada ◽  
Toyohiro Aoki ◽  
Keishi Okamoto ◽  
Shinichi Harada ◽  
John C. Malinowski ◽  
...  
Keyword(s):  
Fine Pitch ◽  
Low K

A novel polymer technology for underfill

2012 ◽  
Vol 1428 ◽  
Author(s):  
Osamu Suzuki ◽  
Toshiyuki Sato ◽  
Paul Czubarow ◽  
David Son
Keyword(s):  
Flip Chip ◽  
Mechanical Analysis ◽  
Reliability Testing ◽  
Hybrid Polymer ◽  
Scanning Calorimetry ◽  
Inorganic Hybrid ◽  
Fine Pitch ◽  
Capillary Type ◽  
Tin Silver Copper ◽  
Low K

AbstractCapillary type underfill is still the mainstream underfill for mass production flip chip applications. Flip chip packages are migrating to ultra low-k, Pb-free, 3D and fine pitch packages. Underfill selection is becoming more critical. This paper discusses the performance and potential of underfills using a novel organic-inorganic hybrid polymer technology.Compared to eutectic and high lead solder, tin-silver-copper solder has lower C.T.E., higher elasticity and greater brittleness. In light of these properties, it is generally better to select high Tg and lower CTE underfill in order to prevent bump fatigue during reliability testing. Given the brittleness of low-k dielectric layers of flip chips, the destruction of low-k layers by stress inside the flip chip packages has become a major issue. Underfills for low-k packages should have low stress, and the warpage should be small. It is expected that as the low-k trend expands, the underfill is required to provide less stress. Low Tg underfill shows lower warpage. New chemical technologies have been developed to address the needs of underfills for low-k/Pb-free flip chip packages, specifically organic-inorganic hybrid polymer compounds. The organic-inorganic hybrid polymer provides excellent cure properties which enable a balanced combination of low stress and good bump protection. The material properties of the underfill were characterized using Differential Scanning Calorimetry (DSC), Thermo-Mechanical Analysis (TMA), and Dynamic Mechanical Analysis (DMA). A daisy-chained test vehicle was used for reliability testing. A detailed study is presented on the underfill properties, reliability data, as well as finite element modeling results.

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