Stress measurements in large area array flip chip microprocessor chips

2008 ◽  
Author(s):  
Jordan C. Roberts ◽  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall ◽  
...  
Keyword(s):  
Flip Chip ◽  
Large Area ◽  
Stress Measurements ◽  
Area Array

Low Stress Under Bump Metallizations for Direct Chip Attach

1998 ◽  
Vol 555 ◽  
Author(s):  
P. Su ◽  
T. M. Korhonen ◽  
S. J. Hong ◽  
M. A. Korhonen ◽  
C. Y. Li
Keyword(s):  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Organic Substrates ◽  
Under Bump Metallization ◽  
Interfacial Failure ◽  
Stress Measurements ◽  
Rapid Reaction

AbstractIn order to use a flip chip method for bonding the Si chip directly to an organic substrate, compatible under bump metallization (UBM) must be available. Conventional schemes with a copper-based solderable layer are not well compatible with the high-tin solders (such as eutectic Pb-Sn) used with organic substrates. This is due to the rapid reaction between Sn and Cu which depletes the UBM of copper. Ni-based schemes exhibit slower reaction with the solder and have been identified by the semiconductor industry as preferable replacements to Cu-based UBM's. However, Ni-containing metallurgies are often associated with high stresses, which results in poor practical adhesion between the silicon chip and the metallization, leading to interfacial failure during fabrication or service. In this research, several nickel-containing UBM schemes are studied experimentally. Stress measurements are made for each metallization before patterning of UBM pads. An optimal Ni concentration for the UBM is suggested based on the results from this study.

Impact of Reprocessing Technique on First Level Interconnects of Pb-Free to SnPb Reballed Area Array Flip Chip Devices

2014 ◽  
Vol 2014 (1) ◽  
pp. 000112-000116
Author(s):  
Joelle Arnold ◽  
Steph Gulbrandsen ◽  
Nathan Blattau
Keyword(s):  
Computer Tomography ◽  
Damage Accumulation ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Acoustic Microscopy ◽  
Eutectic Solder ◽  
X Ray ◽  
Area Array ◽  
Solder Balls ◽  
Commercial Off The Shelf

The risk of damage caused by reballing SnPb eutectic solder balls onto a commercial off-the-shelf (COTS) active flip chip with a ball grid array (BGA) of SAC305 was studied. The effects of reballing performed by five different reballers were examined and compared. The active flip chip device selected included manufacturer specified resistance between eight (8) differential port pairs. The path resistance between these pins following reballing, as compared to an unreballed device, was used to assess damage accumulation in the package. 2-dimensional x-ray microscopy, acoustic microscopy, and x-ray computer tomography were also used to characterize the effects of reballing. These studies indicated that no measureable damage was incurred by the reballing process, implying that reballed devices should function as well as non-reballed devices in the same application.

On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000325-000332 ◽  
Author(s):  
Alan Huffman ◽  
Philip Garrou
Keyword(s):  
Technological Change ◽  
Flip Chip ◽  
Emerging Technologies ◽  
Unit Area ◽  
Form Factors ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Wafer Level Packaging ◽  
Area Array

As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration..

Design, Fabrication, Electrical Characterization and Reliability of Nanomaterials Based Embedded Passives

2010 ◽  
Vol 2010 (1) ◽  
pp. 000847-000854 ◽  
Author(s):  
Rabindra N. Das ◽  
John M. Lauffer ◽  
Steven G. Rosser ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
Thin Film ◽  
Flip Chip ◽  
Electrical Performance ◽  
Large Area ◽  
Capacitance Density ◽  
High Capacitance ◽  
Embedded Passives ◽  
Internal Core ◽  
Embedded Resistors ◽  
Carbon Based

This paper discusses thin film technology based on barium titanate (BaTiO3)-epoxy polymer nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives and their integration in System in a Package (SiP). A variety of nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. Cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. In another design, we have used eight layer high density internal core and subsequent fine geometry n (1 to 3) buildup layers to form a n-8-n structure. The eight layer internal core has two resistance layers in the middle and 2 to 6 capacitance layer sequentially applied on the surface. The study also evaluates the resistor materials for embedded passives. Resistors are carbon based pastes and metal based alloys NiCrAlSi. Embedded resistor technology can use either thin film materials, that are applied on the copper foil, or screened carbon based resistor pastes that can achieve any resistor value at any level. For example, combination of 25 ohm per square material and 250 ohm per square material enables resistor ranges from 15 ohms through 30,000 ohms with efficient sizes for the embedded resistors. Similarly, printable resistors can be designed to cover the resistance in the range of 5 ohms to 1 Mohm. The embedded resistors can be laser trimmed to a tolerance of <5% for applications that require tighter tolerance. Reliability of the test vehicles was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded discrete capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1400 cycles DTC (Deep Thermal Cycle).

A simple modification of a flip‐chip bonder to allow large area chip attach

1999 ◽  
Vol 16 (1) ◽  
pp. 8-11
Author(s):  
S. Fuchs ◽  
K. Rindelhardt ◽  
J. Barrett ◽  
F. Stam
Keyword(s):  
Flip Chip ◽  
Large Area ◽  
Simple Modification

A Multilayer Process for the Connection of Fine-Pitch-Devices on Molded Interconnect Devices (MIDs)

2008 ◽  
Author(s):  
Thomas Leneke ◽  
Soeren Hirsch ◽  
Bertram Schmidt
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Area Array ◽  
Fine Pitch ◽  
Key Factor ◽  
Functional Features ◽  
Escape Routing ◽  
Electrical Connections ◽  
Molded Interconnect Devices ◽  
Metallization Process

A key factor for the propagation of technological applications is the miniaturization of respective components, subsystems and overall systems. To meet future requirements in such size decreasing environments the packaging and mounting technology needs new impulses. 3D-MIDs (three-dimensional molded interconnect devices) exhibit a high potential for smart packages and assemblies. A three-dimensional shaped circuit carrier allows the integration of various functional features (e.g. electrical connections, housing, thermal management, mechanical support). This combination makes a further system shrinking possible. Yet, the mounting of high-density area-array fine-pitch packaged semiconductors (BGA, CSP, MCM) or bare dies to 3D-MIDs is problematic. The lack of a three-dimensional multilayer technology makes a collision free escape routing for devices with a high I/O count difficult. Therefore a new 3D-MID multilayer process was developed and combined with an established 3D-MID metallization process. A demonstrator with three metallization layers, capable, e.g., for flip-chip mounting of area-array packages, is fabricated. The multilayer structure of the demonstrator is investigated with respect to the mechanical and electrical behavior.

Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies

2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mirror Image ◽  
Circuit Board ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Area Array ◽  
Plastic Ball

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.

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