Thermal stability analysis of passive components embedded into printed circuit boards

Purpose The purpose of this paper is to investigate the behavior of embedded passives under changing temperature conditions. Influence of different temperature changes on the basic properties of embedded passives was analyzed. The main reason for these investigations was to determine functionality of passives for space application. Design/methodology/approach The investigations were based on the thin-film resistors made of Ni-P alloy, thick-film resistors made of carbon or carbon-silver inks, embedded capacitors made of FaradFlex materials and embedded inductor made in various configurations. Prepared samples were examined under the influence of a constant elevated temperature (100, 130 or 160°C) in a long period of time (minimum of 30 h), thermal cycles (from −40 to +85°C) or thermal shocks (from −40 to +105°C or from −40 to +125°C). Findings The achieved results revealed that resistance drift became bigger when the samples were treated at a higher constant temperature. At the same time, no significant difference in change in electrical properties for 50 and 100 Ω resistors was noticed. For all the tests, resistance change was below 2 per cent regardless of a value of the tested resistors. Conducted thermal shock studies indicate that thin-film resistors, coils and some thick-film resistors are characterized by minor variations in basic parameters. Some of the inks may show considerable resistance variations with temperature changes. Significant changes were also exhibited by embedded capacitors. Originality/value The knowledge about the behavior of the operating parameters of embedded components considering environmental conditions allow for development of more complex systems with integrated printed circuit boards.

Tolerance-optimized RF structures in LTCC for mm-wave frequencies applications

Low Temperature Co-fired Ceramic (LTCC) is a well established technology for microwave space products and RF structures and it is a good candidate for these new frequency bands. Embedded passives are available to increase the density of integration even more. At higher frequencies structures become smaller and more prone to process tolerances. This challenge is addressed here with two novel mm-wave tolerance-optimized RF concepts in LTCC: load termination and Gysel power splitter. The concept presented here minimizes the effect of fabrication tolerances to provide stable RF response.

Silicon-Embedded RF Micro-Inductors for Ultra-Compact RF Subsystems

Advances in 2.5D and 3D integration technologies are enabling ultra-compact multi-chip modules. In this abstract, we present the design, fabrication, and experimental characterization of RF inductors microfabricated inside deep silicon recesses. Because silicon is often used as a substrate of packaging material for 3D integration and microelectromechanical systems (MEMS), developing microfabrication technologies to embed passive components in the unused volume of the silicon package is a promising approach to realize ultra-compact RF subsystems. Inductors and capacitors are critical in dc-bias circuits for MMICs in order to suppress low-frequency oscillations. Because it is particularly important to have these passive components as close to the MMIC as possible with minimum interconnection parasitics, silicon-embedded passives are an attractive solution. Further, silicon-embedded passives can potentially reduce the overall volume of RF subsystems when compared to modules using discrete passives. Although inductors inside the volume of silicon wafers have previously been reported, they typically operated in the 1–200 MHz frequency range, mostly featuring inductors with wide (50–100 μm) conductors and wide (50–100 μm) interconductor gaps due to fabrication limitations. We first explored process limitations to fabricate structural and electrical features inside 75 to 100-μm-deep silicon cavities. The cavities were etched into the silicon using deep reactive ion etching. Inside these recesses, we demonstrated the fabrication of thin (0.2 μm) and thick (5 μm) gold patterns with 3 μm resolution using lift-off and electroplating processes, respectively. The lift-off process used an image reversal technique, and the plated gold conductors were fabricated through a 6.5-μm-thick photoresist mold. The feature sizes ranged from 3 to 50 μm. For photoresist exposure, an i-line Canon stepper was utilized, and configured specifically to focus at the bottom of the cavities, a key process requirement to achieve high-resolution features. These microfabrication results enabled the design of high-performance RF inductors, which will be discussed in the next section. In addition, we demonstrated the fabrication of 30-μm-deep 3-μm-diameter silicon-etched features inside these cavities, a stepping stone towards achieving high-capacitance-density integrated trench capacitors embedded inside silicon cavities. The silicon-embedded RF inductors were microfabricated on 500-μm-thick high-resistivity (ρ > 20,000 Ω.cm) silicon wafers. First, 75-μm-deep cavities were etched using DRIE. Various two-port coplanar waveguide (CPW) inductor designs were microfabricated. The inductor microfabrication relied on sputtered titanium/gold seed layers, thick AZ4620 photoresist molds, and three 5-μm-thick electroplated gold layers stacked on top of each other to define the inductor conductor and connections. By using a combination of three electroplated layers, high-power-handling low-loss inductors were fabricated. Measurements were performed on a RF probe station, with on-wafer calibration structures. The losses associated with the CPW launchers were de-embedded prior to inductor measurements, and inductor quality factor greater than 40 was measured on various inductors with inductance of approximately 1 nH, and self-resonant frequency at 30 GHz. These results were in agreement with models performed using SONNET simulation package, and are comparable with than that of inductors fabricated on planar silicon wafers.