A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Simultaneous Escape Routing (SER) is the escaping of circuit pins simultaneously from inside two or more pin arrays. This is comparatively difficult as compared to routing in a single array and has not been addressed by previous studies. The increase in pin array complexity has made the manual SER in PCBs a very inefficient and tedious task and there surely is need for the automated routing algorithms. In this work, we propose network flow based optimal algorithm that uses integer linear program to solve SER problem and area routing problem in two stages. In the first stage, pins are escaped to the boundaries of pin arrays simultaneously. These escaped pins are connected with each other in the second stage. The proposed algorithm is tested for different benchmark sizes of grids and the results show that it is not only better in terms of routability but also outperforms existing state of the art algorithms in terms of time consumption. The existing algorithms either fails to achieve higher routability or have larger time complexities, whereas the proposed algorithm achieves 99.9% routability and is also independent of grid topology and component pin arrangement, which shows the superiority of proposed algorithm over the existing algorithms.

Emergency Escape Routing and Evacuation using Bellman Ford’s Algorithm

Evacuation Technique which addresses routing the populaces within the endangered architecture to the bordering emergency-exit points minimizing the mortality rate and avoiding hazards and obstacles at the same time.The fundamental magnitude would be to minimize the risk of total mortality during an emergency condition.The superlative case scenario would be to relinquish all individuals with smidgeon panic and naught transience tempo.This scrutiny will lessen the evacuation time factor by using the deluxe appropriate algorithm available for the shortest path prediction with all of the constraints.