Flip Chip Process Development and Relaibility Evaluation With Lead-Free Solder Alloy

2002 ◽  
Author(s):  
Mohammad Yunus ◽  
Muthiah Venkateswaran ◽  
Peter Borgesen
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
Alpha Particles ◽  
Development Effort ◽  
Test Vehicle ◽  
Initial Development ◽  
Electronic Products ◽  
Semiconductor Chip ◽  
Cu Alloy ◽  
Free Solder

Usually, flipchip technology is based on either high-Pb or eutectic Sn/Pb solder forming the connections between the semiconductor chip and the carrier substrate. However decay of the 210Pb constituent, via 210Bi and 210Po, to 206Pb involves the emission of energetic alpha particles which have a tendency to cause soft errors in nearby active elements on the chip. Also, impending legislations in Europe and Japan on the elimination of Pb from electronic products have prompted the investigation of alternative solder alloys. This paper outlines an initial development effort focussed on the Sn/Ag/Cu (95.8/3.5/0.7) alloy. The study involved the development of a flip chip assembly process followed by a reliability evaluation comparing the fatigue resistance of the Sn/Ag/Cu alloy to that of eutectic Sn/Pb solder. The test vehicle used was a 225μm bump pitch, 11mm square die mounted on a ceramic substrate.

Solid/solid interfacial reactions between Sn–0.7 wt% Cu and Ni–7 wt% V

2008 ◽  
Vol 23 (7) ◽  
pp. 1895-1901 ◽  
Author(s):  
Chih-chi Chen ◽  
Sinn-wen Chen ◽  
Chih-horng Chang
Keyword(s):  
Reaction Time ◽  
Solid State ◽  
Barrier Layer ◽  
Direct Contact ◽  
Flip Chip ◽  
Cu Alloy ◽  
Chip Technology ◽  
Diffusion Barrier Layer ◽  
Free Solder ◽  
State Amorphization

Sn–0.7 wt% Cu alloy is an important Pb-free solder, and Ni–7 wt% V is the major diffusion barrier layer material of flip chip technology. Reactions at the Sn–0.7 wt% Cu/Ni–7 wt% V interface are examined at 160, 180, and 210 °C. Only the Cu6Sn5 phase is formed in the Sn–0.7 wt% Cu/Ni–7 wt% V couple reacted at 160 and 180 °C; however, in addition to the Cu6Sn5 and Ni3Sn4 phases, a quaternary Q phase is formed in the Sn–0.7 wt% Cu/Ni–7 wt% V couple reacted at 210 °C. The Q phase is a mixture of nanocrystalline Ni3Sn4 phase and an amorphous phase. With longer reaction time at 210 °C in the Ni–V/Q/Sn–Cu couple where the Q phase is in direct contact with solder, the Ni3Sn4 phase nucleates inside the preformed Q phase, and the alternating layer phenomenon Ni–V/Q/Ni3Sn4/Q/Ni3Sn4/Cu6Sn5/Sn–Cu is observed. The interesting solid state amorphization and alternating layer phenomena at 210 °C are primarily caused by the fact that Sn and Cu are fast diffusing species, while V is relatively immobile.

Precise Quantitative Evaluation of Nano-Ordered Intermetallic Compounds in Sn-3.0Ag-0.5Cu Lead-Free Solder Bump by Using TEM

2008 ◽  
Vol 47-50 ◽  
pp. 907-911
Author(s):  
Chang Woo Lee ◽  
Y.S. Shin ◽  
J.H. Kim
Keyword(s):  
Intermetallic Compounds ◽  
Flip Chip ◽  
Solder Bump ◽  
Lead Free Solder ◽  
Growth Behaviour ◽  
Sic Particles ◽  
Imcs Growth ◽  
Ordered Intermetallic ◽  
Free Solder ◽  
The One

The growth behaviour of the intermetallic compounds (IMCs) in Pb-free solder bump is investigated. The Pb-free micro-bump, Sn-50%Bi, was fabricated by binary electroplating for flip-chip bond. The diameter of the bump is about 506m and the height is about 60 6m. In order to increase the reliability of the bonding, it is necessary to protect the growth of the IMCs in interface between Cu pad and the solder bump. For control of IMCs growth, SiC particles were distributed in the micro-solder bump during electroplating. The thickness of the IMCs in the interface was estimated by FE-SEM, EDS, XRF and TEM. From the results, The IMCs were found as Cu6Sn5 and Cu3Sn. The thickness of the IMCs decreases with increase the amount of SiC particles until 4 g/cm2. The one candidate of the reasons is that the SiC particles could decrease the area which be reacted between the solder and Cu layer. And another candidate is that the particle can make to difficult inter-diffusion within the interface.

scholarly journals Growth Kinetics of Reaction Layers in Flip Chip Joints with Cu-cored Lead-free Solder Balls

2004 ◽  
Vol 45 (3) ◽  
pp. 754-758 ◽  
Author(s):  
Ikuo Shohji ◽  
Yuji Shiratori ◽  
Hiroshi Yoshida ◽  
Masahiko Mizukami ◽  
Akira Ichida
Keyword(s):  
Growth Kinetics ◽  
Flip Chip ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Balls ◽  
Free Solder ◽  
Kinetics Of Reaction ◽  
Kinetics Of

Establishment of a Competitive Additive Manufacturing Workshop

2016 ◽  
Author(s):  
Paul Ryan ◽  
Jan Schwerdtfeger ◽  
Markus Rodermann
Keyword(s):  
Additive Manufacturing ◽  
Gas Turbines ◽  
High Performance ◽  
Best Practice ◽  
Process Development ◽  
Process Efficiency ◽  
Development Effort ◽  
Industrial Gas Turbines ◽  
High Level ◽  
Design And Manufacture

Compared to conventional manufacturing processes, additive manufacturing offers a degree of freedom that has the potential to revolutionize the turbine components supply chain. Additive manufacturing facilitates the design and manufacture of highly complex components in high performance materials with features that cannot currently be realized with other processes. In addition, shorter development and manufacturing lead-times are possible due to the flexibility of 3D based processing and the absence of expensive, complicated molds or dies. Having been confined for many years to rapid prototyping or R&D applications, additive manufacturing is now making the move to the factory floor. However, a dearth of manufacturing experience makes the development effort and risk of costly mistakes a deterrent for many organizations that would otherwise be interested in exploring the benefits of additive manufacturing. A former manufacturer of industrial gas turbines recently established an additive manufacturing workshop designed to deliver highly complex engine-ready components that can contribute to increased performance of the gas turbine. A strong emphasis on process validation and implementation of the organization’s best practice Lean and Quality methodologies has laid solid foundations for a highly capable manufacturing environment. This paper describes the approach taken to ensure that the workshop achieves a high level of operational excellence. Process development topics explored in the paper include the following: • Planning of process flow and cell layout to permit the maximum lean performance • Strategy used to determine machine specification and selection method. • Assessment of process capability • Influence of design for manufacture on process efficiency and product quality • Experience gained during actual production of first commercial components

Vibration Analysis Based Modeling and Defect Recognition for Flip Chip Solder Joint Inspection

2000 ◽  
Author(s):  
Sheng Liu ◽  
Dathan Erdahl ◽  
I. Charles Ume
Keyword(s):  
Solder Joint ◽  
Vibration Analysis ◽  
Flip Chip ◽  
Process Development ◽  
Great Promise ◽  
Quality Inspection ◽  
Vibration Frequencies ◽  
Vibration Responses ◽  
Solder Joint Inspection ◽  
Joint Quality

Abstract A novel approach for flip chip solder joint quality inspection based on vibration analysis is presented. Traditional solder joint inspection methods have their limitations when applied to flip chip solder joint quality inspection. The vibration detection method is a new approach which has advantages such as being non-contact, non-destructive, fast and can be used on-line or during process development. In this technique, a flip chip was modeled as a thick plate supported by solder bumps. Changes in solder joint quality produce different vibration responses of flip chip, and change its natural vibration frequencies. In this paper, the vibration frequencies of a flip chip on a ceramic substrate were calculated using the finite element method. Based on vibration analysis, a laser ultrasound and interferometric system was developed for flip chip solder joint quality inspection. In this system, chips with good solder joints can be distinguished from chips with bad joints using their vibration responses and frequencies. Defects recognition methods were developed and tested. Results indicate this approach offers great promise for solder bump inspection in flip chip, BGA and chip scale packages.

Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
Short Circuit ◽  
Lead Free Solder ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Different Shapes ◽  
Free Solder ◽  
High Density Packaging

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

Molding Recipe Study for MUF Solder Crack Improvement

2018 ◽  
Vol 2018 (1) ◽  
pp. 000121-000124
Author(s):  
Scott Chen ◽  
Leander Liang ◽  
Pallas Hsu ◽  
Tim Tsai ◽  
Mason Liang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Flow Simulation ◽  
Test Vehicle ◽  
Chip Technology ◽  
Solder Bumps ◽  
Capillary Underfill ◽  
Mold Flow ◽  
Profile Reduction ◽  
Transfer Pressure

Abstract In recent years, flip chip technology becomes more and more important with benefits of thin package profile, reduction of package outline, and excellent electrical and thermal performance by connection of copper pillar bumps (CuP) or C4 solder bumps. In order to fill the die gap to prevent voids problem, two encapsulated solutions could be applied: capillary underfill (CUF) and molded underfill (MUF). In general comparison, CUF means to dispense underfill first to fill in die gap then proceed over-molding afterward; and MUF is directly fill under and above die by mold compound. The advantages of MUF solution are low cost and high throughput, however, it will suffer other assembly issues such as solder extrusion and solder crack, and might result in potential function failure. To form these kinds of defects, we suspected that solder will plastically deform under thermal stress treatment, which comes from unbalance mold transfer pressure and material expansion stress during thermal process. In this article, we have tried to investigate the mechanism of solder crack through molding recipe DOE (Design of Experiment) and mold flow simulation. The test vehicle is 12 × 12 mm2 FCCSP, with 6 × 5 mm2 die size. The bump type is copper pillar bump and pitch/size are 126 um and 35 × 60 um2, respectively. The molding recipe has been evaluated by cross section, and it revealed that molding transfer time and molding temperature are directions toward improvement of solder crack issue.

Sign in / Sign up

Export Citation Format

Share Document