Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking

2006 ◽  
Author(s):  
C. Liu ◽  
V. Iyengar
Keyword(s):  
Network On Chip ◽  
Test Scheduling ◽  
Variable Rate ◽  
Thermal Optimization ◽  
On Chip

scholarly journals ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

2019 ◽  
Vol 9 (2) ◽  
pp. 19 ◽  
Author(s):  
Harikrishna Parmar ◽  
Usha Mehta
Keyword(s):  
Communication Network ◽  
Network On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Power Budget ◽  
Power Efficient ◽  
Efficient Test ◽  
Ip Cores ◽  
On Chip ◽  
The Individual

Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.

scholarly journals A Multi-Verse Optimizer with Levy Flights for Numerical Optimization and Its Application in Test Scheduling for Network-on-Chip

PLoS ONE ◽  
2016 ◽  
Vol 11 (12) ◽  
pp. e0167341 ◽  
Author(s):  
Cong Hu ◽  
Zhi Li ◽  
Tian Zhou ◽  
Aijun Zhu ◽  
Chuanpei Xu
Keyword(s):  
Numerical Optimization ◽  
Network On Chip ◽  
Test Scheduling ◽  
Lévy Flights ◽  
Levy Flights ◽  
On Chip

Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs

2016 ◽  
Author(s):  
Kanchan Manna ◽  
Chatla Swamy Sagar ◽  
Santanu Chattopadhyay ◽  
Indranil Sengupta
Keyword(s):  
Network On Chip ◽  
Test Scheduling ◽  
3D Ics ◽  
On Chip
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