Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks

2014 ◽  
Vol 13 (4s) ◽  
pp. 1-25 ◽  
Author(s):  
Nizar Dahir ◽  
Ra'ed Al-Dujaily ◽  
Terrence Mak ◽  
Alex Yakovlev
Keyword(s):  
Dynamic Programming ◽  
Chip Multiprocessors ◽  
Network On Chip ◽  
Thermal Optimization ◽  
On Chip

Optimal scheduling algorithms of system chip power density based on network on chip

2021 ◽  
pp. 120-127
Author(s):  
Jiashen Li ◽  
◽  
Yun Pan ◽  
Keyword(s):  
Dynamic Programming ◽  
Power Density ◽  
Simulated Annealing Algorithm ◽  
Dynamic Programming Algorithm ◽  
Network On Chip ◽  
Thermal Design ◽  
Optimal Scheduling ◽  
Programming Algorithm ◽  
System Throughput ◽  
On Chip

The improvement of chip integration leads to the increase of power density of system chips, which leads to the overheating of system chips. When dispatching the power density of system chips, some working modules are selectively closed to avoid all modules on the chip being turned on at the same time and to solve the problem of overheating. Taking 2D grid-on-chip network as the research object, an optimal scheduling algorithm of system-on-chip power density based on network-on-chip (NoC) is proposed. Under the constraints of thermal design power (TDP) and system, dynamic programming algorithm is used to solve the optimal application set throughput allocation from bottom to top by dynamic programming for the number and frequency level of each application configuration processor under the given application set of network-on-chip. On this basis, the simulated annealing algorithm is used to complete the application mapping aiming at heat dissipation effect and communication delay. The open and closed processor layout is determined. After obtaining the layout results, the TDP is adjusted. The maximum TDP constraint is iteratively searched according to the feedback loop of the system over-hot spots, and the power density scheduling performance of the system chip is maximized under this constraint, so as to ensure the system core. At the same time, chip throughput can effectively solve the problem of chip overheating. The experimental results show that the proposed algorithm increases the system chip throughput by about 11%, improves the system throughput loss, and achieves a balance between the system chip power consumption and scheduling time.

scholarly journals Static and dynamic task mapping onto network on chip multiprocessors

DYNA ◽  
2014 ◽  
Vol 81 (185) ◽  
pp. 28 ◽  
Author(s):  
Freddy Bolaños-Martínez ◽  
Jose Edison Aedo ◽  
Fredy Rivera-Vélez
Keyword(s):  
Chip Multiprocessors ◽  
Network On Chip ◽  
Task Mapping ◽  
Dynamic Task ◽  
On Chip

Virtualizing network-on-chip resources in chip-multiprocessors

2011 ◽  
Vol 35 (2) ◽  
pp. 230-245 ◽  
Author(s):  
Francisco Triviño ◽  
José L. Sánchez ◽  
Francisco J. Alfaro ◽  
José Flich
Keyword(s):  
Chip Multiprocessors ◽  
Network On Chip ◽  
On Chip

Compiler directed network-on-chip reliability enhancement for chip multiprocessors

2010 ◽  
Vol 45 (4) ◽  
pp. 85-94 ◽  
Author(s):  
Ozcan Ozturk ◽  
Mahmut Kandemir ◽  
Mary J. Irwin ◽  
Sri H.K. Narayanan
Keyword(s):  
Chip Multiprocessors ◽  
Network On Chip ◽  
Directed Network ◽  
Reliability Enhancement ◽  
On Chip

An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors

2016 ◽  
Vol 65 (5) ◽  
pp. 1656-1662 ◽  
Author(s):  
Pejman Lotfi-Kamran ◽  
Mehdi Modarressi ◽  
Hamid Sarbazi-Azad
Keyword(s):  
Chip Multiprocessors ◽  
Network On Chip ◽  
Switched Network ◽  
On Chip
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