Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs

2016 ◽  
Author(s):  
Kanchan Manna ◽  
Chatla Swamy Sagar ◽  
Santanu Chattopadhyay ◽  
Indranil Sengupta
Keyword(s):  
Network On Chip ◽  
Test Scheduling ◽  
3D Ics ◽  
On Chip

Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip

2016 ◽  
Vol 65 (9) ◽  
pp. 2767-2779 ◽  
Author(s):  
Dong Xiang ◽  
Krishnendu Chakrabarty ◽  
Hideo Fujiwara
Keyword(s):  
Network On Chip ◽  
Test Scheduling ◽  
3D Ics ◽  
On Chip

scholarly journals ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

2019 ◽  
Vol 9 (2) ◽  
pp. 19 ◽  
Author(s):  
Harikrishna Parmar ◽  
Usha Mehta
Keyword(s):  
Communication Network ◽  
Network On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Power Budget ◽  
Power Efficient ◽  
Efficient Test ◽  
Ip Cores ◽  
On Chip ◽  
The Individual

Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.

scholarly journals A Multi-Verse Optimizer with Levy Flights for Numerical Optimization and Its Application in Test Scheduling for Network-on-Chip

PLoS ONE ◽  
2016 ◽  
Vol 11 (12) ◽  
pp. e0167341 ◽  
Author(s):  
Cong Hu ◽  
Zhi Li ◽  
Tian Zhou ◽  
Aijun Zhu ◽  
Chuanpei Xu
Keyword(s):  
Numerical Optimization ◽  
Network On Chip ◽  
Test Scheduling ◽  
Lévy Flights ◽  
Levy Flights ◽  
On Chip

scholarly journals Toward Robust Cognitive 3D Brain-Inspired Cross-Paradigm System

2021 ◽  
Vol 15 ◽  
Author(s):  
Abderazek Ben Abdallah ◽  
Khanh N. Dang
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Large Scale ◽  
Three Dimensional ◽  
Network On Chip ◽  
Spike Timing ◽  
Dimensional Structure ◽  
Spiking Neural Network ◽  
3D Ics ◽  
On Chip

Spiking Neuromorphic systems have been introduced as promising platforms for energy-efficient spiking neural network (SNNs) execution. SNNs incorporate neuronal and synaptic states in addition to the variant time scale into their computational model. Since each neuron in these networks is connected to many others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, a precise communication latency is also needed, although SNN is tolerant to the spike delay variation in some limits when it is seen as a whole. The two-dimensional packet-switched network-on-chip was proposed as a solution to provide a scalable interconnect fabric in large-scale spike-based neural networks. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. Combining these two emerging technologies provides a new horizon for IC design to satisfy the high requirements of low power and small footprint in emerging AI applications. Moreover, although fault-tolerance is a natural feature of biological systems, integrating many computation and memory units into neuromorphic chips confronts the reliability issue, where a defective part can affect the overall system's performance. This paper presents the design and simulation of R-NASH-a reliable three-dimensional digital neuromorphic system geared explicitly toward the 3D-ICs biological brain's three-dimensional structure, where information in the network is represented by sparse patterns of spike timing and learning is based on the local spike-timing-dependent-plasticity rule. Our platform enables high integration density and small spike delay of spiking networks and features a scalable design. R-NASH is a design based on the Through-Silicon-Via technology, facilitating spiking neural network implementation on clustered neurons based on Network-on-Chip. We provide a memory interface with the host CPU, allowing for online training and inference of spiking neural networks. Moreover, R-NASH supports fault recovery with graceful performance degradation.

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