Test scheduling for network-on-chip with BIST and precedence constraints

2005 ◽  
Author(s):  
Chunsheng Liu ◽  
E. Cota ◽  
H. Sharif ◽  
D.K. Pradhan
Keyword(s):  
Network On Chip ◽  
Precedence Constraints ◽  
Test Scheduling ◽  
On Chip

scholarly journals ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

2019 ◽  
Vol 9 (2) ◽  
pp. 19 ◽  
Author(s):  
Harikrishna Parmar ◽  
Usha Mehta
Keyword(s):  
Communication Network ◽  
Network On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Power Budget ◽  
Power Efficient ◽  
Efficient Test ◽  
Ip Cores ◽  
On Chip ◽  
The Individual

Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.

scholarly journals A Multi-Verse Optimizer with Levy Flights for Numerical Optimization and Its Application in Test Scheduling for Network-on-Chip

PLoS ONE ◽  
2016 ◽  
Vol 11 (12) ◽  
pp. e0167341 ◽  
Author(s):  
Cong Hu ◽  
Zhi Li ◽  
Tian Zhou ◽  
Aijun Zhu ◽  
Chuanpei Xu
Keyword(s):  
Numerical Optimization ◽  
Network On Chip ◽  
Test Scheduling ◽  
Lévy Flights ◽  
Levy Flights ◽  
On Chip

A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS

2006 ◽  
Vol 06 (04) ◽  
pp. 511-530 ◽  
Author(s):  
HAIDAR M. HARMANANI ◽  
HASSAN A. SALAMY
Keyword(s):  
Simulated Annealing ◽  
Simulated Annealing Algorithm ◽  
System On Chip ◽  
Precedence Constraints ◽  
Test Scheduling ◽  
Optimal Test ◽  
Power Constraints ◽  
Soc Test ◽  
On Chip ◽  
Minimum System

This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs

2016 ◽  
Author(s):  
Kanchan Manna ◽  
Chatla Swamy Sagar ◽  
Santanu Chattopadhyay ◽  
Indranil Sengupta
Keyword(s):  
Network On Chip ◽  
Test Scheduling ◽  
3D Ics ◽  
On Chip
Sign in / Sign up

Export Citation Format

Share Document