Built-in self-test for state faults induced by crosstalk in sequential circuits

Proceedings 10th Asian Test Symposium ◽

10.1109/ats.2001.990336 ◽

2002 ◽

Author(s):

K. Shimizu ◽

N. Itazaki ◽

K. Kinoshita

Keyword(s):

Sequential Circuits ◽

Self Test ◽

Built In Self Test

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On the identification of optimal cellular automata for built-in self-test of sequential circuits

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) ◽

10.1109/vtest.1998.670902 ◽

2002 ◽

Cited By ~ 4

Author(s):

F. Corno ◽

N. Gaudenzi ◽

P. Prinetto ◽

M.S. Reorda

Keyword(s):

Cellular Automata ◽

Sequential Circuits ◽

Self Test ◽

Built In Self Test

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Hybrid built-in self test (BIST) for sequential circuits

2009 Innovative Technologies in Intelligent Systems and Industrial Applications ◽

10.1109/citisia.2009.5224205 ◽

2009 ◽

Cited By ~ 1

Author(s):

Abu Khari bin A'ain ◽

Muhamad Ridzuan bin Radin Muhamad Amin ◽

Mahmud Adnan

Keyword(s):

Sequential Circuits ◽

Self Test ◽

Built In Self Test

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A built-in self-test method for diagnosis of synchronous sequential circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.924046 ◽

2001 ◽

Vol 9 (2) ◽

pp. 290-296 ◽

Cited By ~ 2

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Sequential Circuits ◽

Test Method ◽

Synchronous Sequential Circuits ◽

Self Test ◽

Built In Self Test

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Improved Built-In Self-Test of Sequential Circuits

2007 Canadian Conference on Electrical and Computer Engineering ◽

10.1109/ccece.2007.27 ◽

2007 ◽

Author(s):

Hosna Jabbari ◽

Jon C. Muzio ◽

Lin Sun

Keyword(s):

Sequential Circuits ◽

Self Test ◽

Built In Self Test

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Built-In Self Test of Sequential Circuits

Evolutionary Algorithms for Embedded System Design - Genetic Algorithms and Evolutionary Computation ◽

10.1007/978-1-4615-1035-2_5 ◽

2003 ◽

pp. 143-173

Author(s):

Fulvio Corno ◽

Matteo Sonza Reorda ◽

Giovanni Squillero

Keyword(s):

Sequential Circuits ◽

Self Test ◽

Built In Self Test

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Test the S27 Benchmark Circuit by Using Built In Self Test and Test Pattern Generation

International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering ◽

10.15662/ijareeie.2014.0308083 ◽

2014 ◽

Vol 03 (08) ◽

pp. 11487-11495

Author(s):

S. Nagaraju ◽

Ch.N.L. Sujatha ◽

J.S.S. Ramaraju

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Benchmark Circuit ◽

Self Test ◽

Built In Self Test

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Memory Implementation in a System on Chip with Built-in Self-Test and Recovery Tools

Proceedings of Universities ELECTRONICS ◽

10.24151/1561-5405-2019-24-3-239-247 ◽

2019 ◽

Vol 24 (3) ◽

pp. 239-247

Author(s):

Vladimir G. Ryabtsev ◽

◽

Sergey V. Volobuev ◽

Keyword(s):

System On Chip ◽

Self Test ◽

Built In Self Test ◽

On Chip ◽

Recovery Tools

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RF Phase Error Built-In-Self-Test for A GSM SOC

i-manager’s Journal on Electrical Engineering ◽

10.26634/jee.1.4.378 ◽

2008 ◽

Vol 1 (4) ◽

pp. 39-44

Author(s):

Dallas Webster ◽

Loi Phan ◽

Oren Eliezer ◽

Rick Hudgens ◽

Donald Lie

Keyword(s):

Phase Error ◽

Self Test ◽

Built In Self Test

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Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/3427911 ◽

2021 ◽

Vol 26 (3) ◽

pp. 1-18

Author(s):

Mehmet Ince ◽

Ender Yilmaz ◽

Wei Fu ◽

Joonsung Park ◽

Krishnaswamy Nagaraj ◽

...

Keyword(s):

Phase Locked Loops ◽

Test And Evaluation ◽

Self Test ◽

Built In Self Test

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IBIST/sup TM/ (interconnect built-in self-test) architecture and methodology for pci express: intel's next-generation test and validation methodology for performance IO

International Test Conference, 2003. Proceedings. ITC 2003. ◽

10.1109/test.2003.1270909 ◽

2004 ◽

Cited By ~ 5

Author(s):

J.J. Nejedlo

Keyword(s):

Next Generation ◽

Pci Express ◽

Self Test ◽

Built In Self Test ◽

Test Architecture ◽

Generation Test

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