Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

2021 ◽  
Vol 26 (3) ◽  
pp. 1-18
Author(s):  
Mehmet Ince ◽  
Ender Yilmaz ◽  
Wei Fu ◽  
Joonsung Park ◽  
Krishnaswamy Nagaraj ◽  
...  
Keyword(s):  
Phase Locked Loops ◽  
Test And Evaluation ◽  
Self Test ◽  
Built In Self Test

Built-In Self-Test for Phase-Locked Loops

2005 ◽  
Vol 54 (3) ◽  
pp. 996-1002 ◽  
Author(s):  
C.-L. Hsu ◽  
Y. Lai ◽  
S.-W. Wang
Keyword(s):  
Phase Locked Loops ◽  
Self Test ◽  
Built In Self Test

Built-In Self-Test Scheme for All-Digital Phase-Locked Loops

2012 ◽  
Vol 546-547 ◽  
pp. 922-927
Author(s):  
Zhi Kuang Cai ◽  
Kai Huang ◽  
Jun Yang ◽  
Long Xing Shi
Keyword(s):  
Low Cost ◽  
Digital Design ◽  
Design Flow ◽  
Phase Locked Loops ◽  
Test Scheme ◽  
Parity Check ◽  
Digital Signals ◽  
Self Test ◽  
Built In Self Test ◽  
Hybrid Faults

This paper presents a low-cost Built-In Self-Test (BIST) scheme, which is based on the principle of parity check code. The proposed circuit is consisted of a XOR network, a frequency decrease module, a BIST controller and a fault detector module. Different from the previous methods of PLL BIST, digital signals from the divide-by-N are grouped as transmission codes, and parity check codes are produced synchronously by the BIST controller. Then the results of parity checking are imported to the fault detector and final test results are generated. Purely digital design flow is adopted and hybrid faults models are used to evaluate the efficiency of the circuit. Experimental results indicates that the proposed method can provide the highest test coverage and lower area overhead, which are 98.3% and 4.2%, respectively.

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