An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits

2002 ◽  
Author(s):  
D.R. Chakrabarti ◽  
A. Jain
Keyword(s):  
Test Generation ◽  
Combinational Circuits ◽  
Generation Technique

Hierarchical test generation for combinational circuits with real defects coverage

2002 ◽  
Vol 42 (7) ◽  
pp. 1141-1149 ◽  
Author(s):  
T Cibáková ◽  
M Fischerová ◽  
E Gramatová ◽  
W Kuzmicz ◽  
W.A Pleskacz ◽  
...  
Keyword(s):  
Test Generation ◽  
Combinational Circuits

scholarly journals Testability-Driven Layout of Combinational Circuits

VLSI Design ◽  
1998 ◽  
Vol 7 (4) ◽  
pp. 347-352
Author(s):  
C. P. Ravikumar ◽  
Nikhil Sharma
Keyword(s):  
Test Generation ◽  
Test Pattern ◽  
Pattern Generator ◽  
Test Vector ◽  
Combinational Circuits ◽  
Bridging Faults ◽  
Cpu Time ◽  
On Line ◽  
Placement Algorithm ◽  
Automatic Test Pattern Generator

The layout of a circuit can influence the probability of occurrence of faults. In this paper, we develop algorithms that can take advantage of this fact to reduce the chances of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is common practice to drop such HTD faults from consideration during test generation. The chip fault coverage achieved by a test set is poor if the fault set consists of many HTD faults. We can combat this problem by avoiding altogether, or by reducing the probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect bridging faults and show how module placement rules can be derived to reduce the probability of these faults. A genetic placement algorithm that optimizes area while respecting these rules is presented. The placement algorithm has been implemented for standard-cell layout style on a SUN/SPARC and tested against several sample circuits.

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