2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781467328999, 9781467328975, 9781467328982

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Energy aware TLM platform simulation via RTL abstraction

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2012.6418258 ◽

2012 ◽

Cited By ~ 2

Author(s):

Nicola Bombieri ◽

Franco Fummi ◽

Valerio Guarnieri ◽

Andrea Acquaviva

Keyword(s):

Energy Aware

Download Full-text

A functional test generation technique for RTL datapaths

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2012.6418244 ◽

2012 ◽

Cited By ~ 1

Author(s):

Bijan Alizadeh ◽

Masahiro Fujita

Keyword(s):

Test Generation ◽

Functional Test ◽

Generation Technique

Download Full-text

The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2012.6418246 ◽

2012 ◽

Cited By ~ 1

Author(s):

Diego Braga ◽

Franco Fummi ◽

Graziano Pravadelli ◽

Sara Vinco

Keyword(s):

Embedded Systems

Download Full-text

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2012.6418233 ◽

2012 ◽

Download Full-text

Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2012.6418239 ◽

2012 ◽

Author(s):

Freek Verbeek ◽

Julien Schmaltz

Keyword(s):

Automatic Generation ◽

Deadlock Detection ◽

Detection Algorithms ◽

Description Languages

Download Full-text

Monitoring distributed reactive systems

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2012.6418247 ◽

2012 ◽

Cited By ~ 1

Author(s):

Yu Bai ◽

Jens Brandt ◽

Klaus Schneider

Keyword(s):

Reactive Systems

Download Full-text

Post-silicon verification and debugging with control flow traces and patchable hardware

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2012.6418250 ◽

2012 ◽

Author(s):

Masahiro Fujita

Keyword(s):

Control Flow ◽

Silicon Verification

Download Full-text

Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2012.6418236 ◽

2012 ◽

Author(s):

Huy Nguyen ◽

Michael S. Hsiao

Keyword(s):

Equivalence Checking ◽

Inductive Invariants ◽

Sequential Equivalence Checking

Download Full-text

Using haloes in mixed-signal assertion based verification

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2012.6418242 ◽

2012 ◽

Cited By ~ 2

Author(s):

Dogan Ulus ◽

Alper Sen

Keyword(s):

Mixed Signal

Download Full-text

A formal method to improve SystemVerilog functional coverage

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2012.6418243 ◽

2012 ◽

Cited By ~ 1

Author(s):

An-Che Cheng ◽

Chia-Chih Yen ◽

Jing-Yang Jou

Keyword(s):

Formal Method ◽

Functional Coverage

Download Full-text

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Energy aware TLM platform simulation via RTL abstraction

A functional test generation technique for RTL datapaths

The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems

Table of contents

Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics

Monitoring distributed reactive systems

Post-silicon verification and debugging with control flow traces and patchable hardware

Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies

Using haloes in mixed-signal assertion based verification

A formal method to improve SystemVerilog functional coverage

Export Citation Format

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Energy aware TLM platform simulation via RTL abstraction

A functional test generation technique for RTL datapaths

The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems

Table of contents

Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics

Monitoring distributed reactive systems

Post-silicon verification and debugging with control flow traces and patchable hardware

Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies

Using haloes in mixed-signal assertion based verification

A formal method to improve SystemVerilog functional coverage

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)
Latest Publications