Proceedings of IEEE 3rd Asian Test Symposium (ATS)
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Published By IEEE Comput. Soc. Press

0818666900

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An approach of diagnosing single bridging faults in CMOS combinational circuits

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367248 ◽

2002 ◽

Cited By ~ 5

Author(s):

K. Yamazaki ◽

T. Yamada

Keyword(s):

Combinational Circuits ◽

Bridging Faults

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A unified model for inter-gate and intra-gate CMOS bridging fault: the configuration ratio

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367235 ◽

2002 ◽

Cited By ~ 6

Author(s):

M. Renovell ◽

P. Huc ◽

Y. Bertrand

Keyword(s):

Unified Model ◽

Bridging Fault

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Fault diagnosis technique for subranging ADCs

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367204 ◽

2002 ◽

Cited By ~ 5

Author(s):

A. Charoenrook ◽

M. Soma

Keyword(s):

Fault Diagnosis ◽

Diagnosis Technique

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A built-in self-test approach for medium to high-resolution digital-to-analog converters

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367203 ◽

2002 ◽

Cited By ~ 3

Author(s):

K. Arabi ◽

B. Kaminska ◽

J. Rzeszut

Keyword(s):

High Resolution ◽

Digital To Analog Converters ◽

Self Test ◽

Built In Self Test ◽

Digital To Analog

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Design of random pattern testable floating point adders

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367226 ◽

2002 ◽

Cited By ~ 3

Author(s):

J. Rajski ◽

J. Tyszer

Keyword(s):

Floating Point ◽

Random Pattern

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Detectability of spurious signals with limited propagation in combinational circuits

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367232 ◽

2002 ◽

Cited By ~ 5

Author(s):

F. Moll ◽

M. Roca ◽

D. Marche ◽

A. Rubio

Keyword(s):

Combinational Circuits ◽

Spurious Signals

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A built-in I/sub DDQ/ test circuit utilizing upper and lower limits

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367240 ◽

2002 ◽

Cited By ~ 4

Author(s):

Y. Miura ◽

S. Naito

Keyword(s):

Test Circuit ◽

Lower Limits

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To verify manufacturing yield by testing

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367201 ◽

2002 ◽

Author(s):

Mill-Jer Wang ◽

Jwu-E Chen ◽

Yung-Yuan Chen

Keyword(s):

Manufacturing Yield

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Design of pseudo-random patterns with low linear dependence and equi-distribution

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367219 ◽

2002 ◽

Author(s):

S. Matsufuji ◽

S.-I. Tadaki ◽

T. Yamanaka

Keyword(s):

Linear Dependence ◽

Random Patterns

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On the performance analysis of parallel processing for test generation

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367251 ◽

2002 ◽

Cited By ~ 1

Author(s):

T. Inoue ◽

T. Fujii ◽

H. Fujiwara

Keyword(s):

Parallel Processing ◽

Performance Analysis ◽

Test Generation

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Proceedings of IEEE 3rd Asian Test Symposium (ATS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

An approach of diagnosing single bridging faults in CMOS combinational circuits

A unified model for inter-gate and intra-gate CMOS bridging fault: the configuration ratio

Fault diagnosis technique for subranging ADCs

A built-in self-test approach for medium to high-resolution digital-to-analog converters

Design of random pattern testable floating point adders

Detectability of spurious signals with limited propagation in combinational circuits

A built-in I/sub DDQ/ test circuit utilizing upper and lower limits

To verify manufacturing yield by testing

Design of pseudo-random patterns with low linear dependence and equi-distribution

On the performance analysis of parallel processing for test generation

Proceedings of IEEE 3rd Asian Test Symposium (ATS)
Latest Publications