NEST: a nonenumerative test generation method for path delay faults in combinational circuits

I. Pomeranz; S.M. Reddy; P. Uppaluri

doi:10.1109/43.476581

NEST: a nonenumerative test generation method for path delay faults in combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.476581 ◽

1995 ◽

Vol 14 (12) ◽

pp. 1505-1515 ◽

Cited By ~ 30

Author(s):

I. Pomeranz ◽

S.M. Reddy ◽

P. Uppaluri

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults

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An efficient automatic test generation system for path delay faults in combinational circuits

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512097 ◽

2002 ◽

Cited By ~ 12

Author(s):

A.K. Majhi ◽

J. Jacob ◽

L.M. Patnaik ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults ◽

Generation System ◽

Automatic Test Generation ◽

Automatic Test

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Test generation for primitive path delay faults in combinational circuits

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97 ◽

10.1109/iccad.1997.643605 ◽

1997 ◽

Cited By ~ 15

Author(s):

Tekumalla ◽

Menon

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults

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A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Cited By ~ 30

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults

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Deterministic broadside test generation for transition path delay faults

Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10 ◽

10.1145/1785481.1785514 ◽

2010 ◽

Cited By ~ 1

Author(s):

Bo Yao ◽

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Transition Path

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A method to derive compact test sets for path delay faults in combinational circuits

Proceedings of IEEE International Test Conference - (ITC) ◽

10.1109/test.1993.470630 ◽

2002 ◽

Cited By ~ 27

Author(s):

J. Saxena ◽

D.K. Pradhan

Keyword(s):

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults ◽

Test Sets ◽

Compact Test

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Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.81 ◽

2007 ◽

Cited By ~ 2

Author(s):

Rajsekhar Adapa ◽

Edward Flanigan ◽

Spyros Tragoudas ◽

Michael Laisne ◽

Hailong Cui ◽

...

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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A test generation system for path delay faults

Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1989.63324 ◽

2003 ◽

Cited By ~ 23

Author(s):

S. Patil ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Generation System

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Test generation for path delay faults based on learning

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1993.580092 ◽

2002 ◽

Cited By ~ 7

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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Robust test generation for power supply noise induced path delay faults

2008 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2008.4484033 ◽

2008 ◽

Cited By ~ 1

Author(s):

Xiang Fu ◽

Huawei Li ◽

Yu Hu ◽

Xiaowei Li

Keyword(s):

Power Supply ◽

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Power Supply Noise ◽

Path Delay Faults ◽

Robust Test ◽

Supply Noise ◽

Induced Path

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A simulator for at-speed robust testing of path delay faults in combinational circuits

IEEE Transactions on Computers ◽

10.1109/12.544489 ◽

1996 ◽

Vol 45 (11) ◽

pp. 1312-1318 ◽

Cited By ~ 6

Author(s):

Yuan-Chieh Hsu ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults ◽

Robust Testing

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