Proceedings of the 8th International Conference on VLSI Design
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Published By IEEE Comput. Soc. Press

0818669055

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A new switching-level approach to multiple-output functions synthesis

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512090 ◽

2002 ◽

Cited By ~ 2

Author(s):

C. Bolchini ◽

G. Buonanno ◽

D. Sciuto ◽

R. Stefanelli

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A VLSI architecture for the computation of NURBS patches

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512133 ◽

2002 ◽

Cited By ~ 1

Author(s):

M.S. Gopi ◽

S. Manohar

Keyword(s):

Vlsi Architecture

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A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512105 ◽

2002 ◽

Author(s):

V. Puvvada ◽

S. Potla ◽

T. Selvam ◽

P.R. Suresh

Keyword(s):

Simulation Study ◽

Cmos Technology

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An improved output compaction technique for built-in self-test in VLSI circuits

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512147 ◽

2002 ◽

Cited By ~ 14

Author(s):

S.R. Das ◽

H.T. Ho ◽

W.-B. Jone ◽

A.R. Nayak

Keyword(s):

Vlsi Circuits ◽

Self Test ◽

Built In Self Test

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Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512078 ◽

2002 ◽

Author(s):

S. Chattopadhyay ◽

S. Roy ◽

P. Pal Chaudhuri

Keyword(s):

Cellular Automata ◽

Technology Mapping ◽

Fpga Architecture ◽

Logic Module

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A general graph theoretic framework for multi-layer channel routing

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512109 ◽

2002 ◽

Cited By ~ 11

Author(s):

R.K. Pal ◽

A.K. Datta ◽

S.P. Pal ◽

M.M. Das ◽

A. Pal

Keyword(s):

Channel Routing ◽

General Graph ◽

Graph Theoretic

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A differential built-in current sensor design for high speed IDDQ testing

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512150 ◽

2002 ◽

Cited By ~ 8

Author(s):

J.P. Hurst ◽

A.D. Singh

Keyword(s):

High Speed ◽

Current Sensor ◽

Sensor Design ◽

Iddq Testing

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Fast computation of MISR signatures

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512149 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Franklin ◽

K.K. Saluja ◽

K. Kim

Keyword(s):

Fast Computation

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Wave pipelined architecture folding: a method to achieve low power and low area

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512102 ◽

2002 ◽

Cited By ~ 1

Author(s):

D. Ghosh ◽

S.K. Nandy

Keyword(s):

Low Power ◽

Low Area ◽

Pipelined Architecture

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An efficient automatic test generation system for path delay faults in combinational circuits

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512097 ◽

2002 ◽

Cited By ~ 12

Author(s):

A.K. Majhi ◽

J. Jacob ◽

L.M. Patnaik ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults ◽

Generation System ◽

Automatic Test Generation ◽

Automatic Test

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Proceedings of the 8th International Conference on VLSI DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

A new switching-level approach to multiple-output functions synthesis

A VLSI architecture for the computation of NURBS patches

A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology

An improved output compaction technique for built-in self-test in VLSI circuits

Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture

A general graph theoretic framework for multi-layer channel routing

A differential built-in current sensor design for high speed IDDQ testing

Fast computation of MISR signatures

Wave pipelined architecture folding: a method to achieve low power and low area

An efficient automatic test generation system for path delay faults in combinational circuits

Proceedings of the 8th International Conference on VLSI Design
Latest Publications