scholarly journals Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks

2009 ◽  
Author(s):  
William Toms ◽  
Doug Edwards
Keyword(s):  
Synthesis Method ◽  
Combinational Logic ◽  
Logic Blocks

scholarly journals Technology Mapping of FSM Oriented to LUT-Based FPGA

2020 ◽  
Vol 10 (11) ◽  
pp. 3926
Author(s):  
Marcin Kubica ◽  
Dariusz Kania
Keyword(s):  
Field Programmable Gate Array ◽  
Finite State Machine ◽  
Synthesis Method ◽  
Technology Mapping ◽  
Look Up Table ◽  
Finite State ◽  
Field Programmable ◽  
Simultaneous Synthesis ◽  
Transition Block ◽  
Logic Blocks

The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped in LUT-based logic blocks. In the paper, the idea of carrying out the combinational part of FSM was presented and leads to the reduction of the number of LUTs needed to carry out an automaton. The essence of this method is a simultaneous synthesis of the whole combinational block described in the form of multi-output function. The proposed idea makes it possible to conduct decomposition that may enable to share logic blocks, which can lead to the reduction of using resources of FPGA. The decomposition process was conducted using the analyzed DECOMP system. The effectiveness of the proposed idea of the FSM description was also confirmed by conducting decomposition with the usage of the ABC system. The obtained results prove the efficiency of the proposed synthesis method of FSM in comparison with the separate synthesis of a transition block and an output block.

scholarly journals Area–Oriented Technology Mapping for LUT–Based Logic Blocks

2017 ◽  
Vol 27 (1) ◽  
pp. 207-222 ◽  
Author(s):  
Marcin Kubica ◽  
Dariusz Kania
Keyword(s):  
Synthesis Method ◽  
Logic Synthesis ◽  
Experimental Results ◽  
Technology Mapping ◽  
Decomposition Technique ◽  
Experimental Section ◽  
Logic Optimization ◽  
Mapping Strategy ◽  
Novel Theory ◽  
Logic Blocks

Abstract One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

scholarly journals A Modified Approach to Test Plan Generation for Combinational Logic Blocks

VLSI Design ◽  
1996 ◽  
Vol 4 (3) ◽  
pp. 243-256
Author(s):  
Anupam Basu ◽  
Dilip K. Banerji ◽  
Amit Basu ◽  
T. C. Wilson ◽  
Jay C. Majithia
Keyword(s):  
Vlsi Circuits ◽  
Testing Time ◽  
Combinational Logic ◽  
Test Plan ◽  
Crucial Step ◽  
Plan Generation ◽  
Test Methodology ◽  
Test Plan Generation ◽  
Total Testing Time ◽  
Logic Blocks

Generation of test plans is a crucial step for testing VLSI circuits. This paper presents a modified approach to test plan generation for the BILBO test methodology. A few limitations of the existing approaches have been identified and methods to address these have been suggested. The proposed approach has been implemented for the general case of n-port combinational logic blocks (CLBs). However, due to limitations of space and for clarity, only 2-port CLBs are considered in this paper. For this case, the problem is modelled as a Step Scheduling Matrix and an algorithm is presented for the solution. The algorithm has been tested on a number of benchmark circuits and the results are compared with those obtained through existing methods. The effectiveness of the proposed approach is clear from the results, as it contributes to the reduction in total testing time as well as generates a larger number of test plans.

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