Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference
Latest Publications

TOTAL DOCUMENTS

124

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0780336623

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

VIDE: a visual VHDL integrated design environment

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1997.600258 ◽

2002 ◽

Cited By ~ 1

Author(s):

Jinian Bian ◽

Hongxi Xue ◽

Ming Su

Keyword(s):

Integrated Design ◽

Design Environment ◽

Integrated Design Environment

Download Full-text

Trade-off evaluation in embedded system design via co-simulation

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1997.600159 ◽

2002 ◽

Cited By ~ 9

Author(s):

C. Passerone ◽

L. Lavagno ◽

C. Sansoe ◽

M. Chiodo ◽

A. Sangiovanni-Vincentelli

Keyword(s):

Embedded System ◽

System Design ◽

Trade Off ◽

Embedded System Design

Download Full-text

A quantitative analysis for optimizing memory allocation

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1997.600131 ◽

2002 ◽

Author(s):

Youn-Sik Hong ◽

Choong-Hee Cho ◽

D.D. Gajski

Keyword(s):

Quantitative Analysis ◽

Memory Allocation

Download Full-text

Fault coverage improvement based on error signal analysis

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1997.600274 ◽

2002 ◽

Author(s):

M.W.T. Wong ◽

Yingquan Zhou ◽

Y.S. Lee ◽

Yinghua Min

Keyword(s):

Signal Analysis ◽

Fault Coverage ◽

Error Signal

Download Full-text

VEAP: Global optimization based efficient algorithm for VLSI placement

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1997.600151 ◽

2002 ◽

Cited By ~ 1

Author(s):

Kong Tianming ◽

Hong Xianlong ◽

Qiao Changge

Keyword(s):

Global Optimization ◽

Efficient Algorithm

Download Full-text

Built-in chaining: introducing complex components into architectural synthesis

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1997.600342 ◽

2002 ◽

Cited By ~ 19

Author(s):

P. Marwedel ◽

B. Landwehr ◽

R. Domer

Keyword(s):

Architectural Synthesis ◽

Complex Components

Download Full-text

±1.5 V CMOS four-quadrant multiplier

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1997.600283 ◽

2002 ◽

Author(s):

S.C. Li

Keyword(s):

Four Quadrant

Download Full-text

A rapid prototyping method for top-down design of system-on-chip devices using LPGAs

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1997.600051 ◽

2002 ◽

Cited By ~ 1

Author(s):

F. Suzuki ◽

H. Koizumi ◽

K. Seo ◽

H. Yasuura ◽

M. Hiramine ◽

...

Keyword(s):

Rapid Prototyping ◽

System On Chip ◽

Top Down ◽

On Chip

Download Full-text

Performance test of Viterbi decoder for wideband CDMA system

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1997.600052 ◽

2002 ◽

Cited By ~ 2

Author(s):

Jang-Hyun Park ◽

Yea-Chul Rho

Keyword(s):

Performance Test ◽

Cdma System ◽

Viterbi Decoder ◽

Wideband Cdma

Download Full-text

Parallel calculation of 3-D parasitic resistance and capacitance with linear boundary elements

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.1997.600200 ◽

2002 ◽

Author(s):

Wenming Zhou ◽

Zeyi Wang ◽

Lan Rao

Keyword(s):

Boundary Elements ◽

Linear Boundary ◽

Parallel Calculation ◽

Parasitic Resistance

Download Full-text

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation ConferenceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

VIDE: a visual VHDL integrated design environment

Trade-off evaluation in embedded system design via co-simulation

A quantitative analysis for optimizing memory allocation

Fault coverage improvement based on error signal analysis

VEAP: Global optimization based efficient algorithm for VLSI placement

Built-in chaining: introducing complex components into architectural synthesis

±1.5 V CMOS four-quadrant multiplier

A rapid prototyping method for top-down design of system-on-chip devices using LPGAs

Performance test of Viterbi decoder for wideband CDMA system

Parallel calculation of 3-D parasitic resistance and capacitance with linear boundary elements

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference
Latest Publications