A hierarchical based approach for coupling aware delay analysis of combinational logic blocks

2002 ◽  
Author(s):  
Ninglong Lu ◽  
I.N. Hajj
Keyword(s):  
Delay Analysis ◽  
Combinational Logic ◽  
Logic Blocks

scholarly journals A Modified Approach to Test Plan Generation for Combinational Logic Blocks

VLSI Design ◽  
1996 ◽  
Vol 4 (3) ◽  
pp. 243-256
Author(s):  
Anupam Basu ◽  
Dilip K. Banerji ◽  
Amit Basu ◽  
T. C. Wilson ◽  
Jay C. Majithia
Keyword(s):  
Vlsi Circuits ◽  
Testing Time ◽  
Combinational Logic ◽  
Test Plan ◽  
Crucial Step ◽  
Plan Generation ◽  
Test Methodology ◽  
Test Plan Generation ◽  
Total Testing Time ◽  
Logic Blocks

Generation of test plans is a crucial step for testing VLSI circuits. This paper presents a modified approach to test plan generation for the BILBO test methodology. A few limitations of the existing approaches have been identified and methods to address these have been suggested. The proposed approach has been implemented for the general case of n-port combinational logic blocks (CLBs). However, due to limitations of space and for clarity, only 2-port CLBs are considered in this paper. For this case, the problem is modelled as a Step Scheduling Matrix and an algorithm is presented for the solution. The algorithm has been tested on a number of benchmark circuits and the results are compared with those obtained through existing methods. The effectiveness of the proposed approach is clear from the results, as it contributes to the reduction in total testing time as well as generates a larger number of test plans.

Combinational Logic Analysis Using Laser Voltage Probing

2015 ◽  
Author(s):  
Venkat Krishnan Ravikumar ◽  
Winson Lua ◽  
Seah Yi Xuan ◽  
Gopinath Ranganathan ◽  
Angeline Phoa
Keyword(s):  
Failure Analysis ◽  
Continuous Wave ◽  
Truth Table ◽  
Combinational Logic ◽  
Infra Red ◽  
Analysis Design ◽  
Logic State

Abstract Laser Voltage Probing (LVP) using continuous-wave near infra-red lasers are popular for failure analysis, design and test debug. LVP waveforms provide information on the logic state of the circuitry. This paper aims to explain the waveforms observed from combinational circuitries and use it to rebuild the truth table.

Delay analysis for IEEE 802.11 DCF mechanism in finite load

2011 ◽  
Vol 25 (2) ◽  
pp. 176-180
Author(s):  
Benhong Zhang ◽  
Yang Lu ◽  
Qilin Wu ◽  
Yan Zhai
Keyword(s):  
Ieee 802.11 ◽  
Delay Analysis ◽  
Ieee 802.11 Dcf ◽  
802.11 Dcf ◽  
Finite Load
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