scholarly journals A Modified Approach to Test Plan Generation for Combinational Logic Blocks

VLSI Design ◽  
1996 ◽  
Vol 4 (3) ◽  
pp. 243-256
Author(s):  
Anupam Basu ◽  
Dilip K. Banerji ◽  
Amit Basu ◽  
T. C. Wilson ◽  
Jay C. Majithia
Keyword(s):  
Vlsi Circuits ◽  
Testing Time ◽  
Combinational Logic ◽  
Test Plan ◽  
Crucial Step ◽  
Plan Generation ◽  
Test Methodology ◽  
Test Plan Generation ◽  
Total Testing Time ◽  
Logic Blocks

Generation of test plans is a crucial step for testing VLSI circuits. This paper presents a modified approach to test plan generation for the BILBO test methodology. A few limitations of the existing approaches have been identified and methods to address these have been suggested. The proposed approach has been implemented for the general case of n-port combinational logic blocks (CLBs). However, due to limitations of space and for clarity, only 2-port CLBs are considered in this paper. For this case, the problem is modelled as a Step Scheduling Matrix and an algorithm is presented for the solution. The algorithm has been tested on a number of benchmark circuits and the results are compared with those obtained through existing methods. The effectiveness of the proposed approach is clear from the results, as it contributes to the reduction in total testing time as well as generates a larger number of test plans.

scholarly journals EXPERT SYSTEMS AND TEST PLAN GENERATION

1990 ◽  
Author(s):  
ΙΩΑΝΝΗΣ ΠΑΠΑΒΑΣΙΛΕΙΟΥ
Keyword(s):  
Expert Systems ◽  
Test Plan ◽  
Plan Generation ◽  
Test Plan Generation

Determination of Steady-State Adhesive Wear Rate

2005 ◽  
Author(s):  
L. J. Yang
Keyword(s):  
Steady State ◽  
Wear Rate ◽  
Wear Test ◽  
Standard Test ◽  
Test Method ◽  
Testing Time ◽  
Wear Coefficient ◽  
Wear Rates ◽  
Test Methodology

Wear rates obtained from different investigators could vary significantly due to lack of a standard test method. A test methodology is therefore proposed in this paper to enable the steady-state wear rate to be determined more accurately, consistently, and efficiently. The wear test will be divided into four stages: (i) to conduct the transient wear test; (ii) to predict the steady-state wear coefficient with the required sliding distance based on the transient wear data by using Yang’s second wear coefficient equation; (iii) to conduct confirmation runs to obtain the measured steady-state wear coefficient value; and (iv) to convert the steady-state wear coefficient value into a steady-state wear rate. The proposed methodology is supported by wear data obtained previously on aluminium based matrix composite materials. It is capable of giving more accurate steady-state wear coefficient and wear rate values, as well as saving a lot of testing time and labour, by reducing the number of trial runs required to achieve the steady-state wear condition.

FAULT TOLERANCE AND DETECTION IN CHAOTIC COMPUTERS

2007 ◽  
Vol 17 (06) ◽  
pp. 1955-1968 ◽  
Author(s):  
MOHAMMAD R. JAHED-MOTLAGH ◽  
BEHNAM KIA ◽  
WILLIAM L. DITTO ◽  
SUDESHNA SINHA
Keyword(s):  
Chaotic Systems ◽  
Chaotic Maps ◽  
Structural Testing ◽  
Testing Time ◽  
Computing Device ◽  
One Dimensional ◽  
Testing Method ◽  
Higher Dimensional ◽  
Parameter Variations ◽  
Logic Blocks

We introduce a structural testing method for a dynamics based computing device. Our scheme detects different physical defects, manifesting themselves as parameter variations in the chaotic system at the core of the logic blocks. Since this testing method exploits the dynamical properties of chaotic systems to detect damaged logic blocks, the damaged elements can be detected by very few testing inputs, leading to very low testing time. Further the method does not entail dedicated or extra hardware for testing. Specifically, we demonstrate the method on one-dimensional unimodal chaotic maps. Some ideas for testing higher dimensional maps and flows are also presented.

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