scholarly journals Technology Mapping of FSM Oriented to LUT-Based FPGA

2020 ◽  
Vol 10 (11) ◽  
pp. 3926
Author(s):  
Marcin Kubica ◽  
Dariusz Kania
Keyword(s):  
Field Programmable Gate Array ◽  
Finite State Machine ◽  
Synthesis Method ◽  
Technology Mapping ◽  
Look Up Table ◽  
Finite State ◽  
Field Programmable ◽  
Simultaneous Synthesis ◽  
Transition Block ◽  
Logic Blocks

The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped in LUT-based logic blocks. In the paper, the idea of carrying out the combinational part of FSM was presented and leads to the reduction of the number of LUTs needed to carry out an automaton. The essence of this method is a simultaneous synthesis of the whole combinational block described in the form of multi-output function. The proposed idea makes it possible to conduct decomposition that may enable to share logic blocks, which can lead to the reduction of using resources of FPGA. The decomposition process was conducted using the analyzed DECOMP system. The effectiveness of the proposed idea of the FSM description was also confirmed by conducting decomposition with the usage of the ABC system. The obtained results prove the efficiency of the proposed synthesis method of FSM in comparison with the separate synthesis of a transition block and an output block.

scholarly journals VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

2021 ◽  
Vol 14 (1) ◽  
pp. 22-31
Author(s):  
Kommalapati Monica ◽  
◽  
Dereddy Anuradha ◽  
Syed Rasheed ◽  
Barnala Shereesha ◽  
...  
Keyword(s):  
Power Consumption ◽  
Field Programmable Gate Array ◽  
Finite Impulse Response ◽  
Research Work ◽  
Industrial Applications ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Look Up Table ◽  
Field Programmable ◽  
Wallace Tree Multiplier

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

scholarly journals FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach

2019 ◽  
Vol 2019 ◽  
pp. 1-17 ◽  
Author(s):  
Nitish Das ◽  
Aruna Priya P
Keyword(s):  
Barrier Function ◽  
Gradient Descent ◽  
Finite State Machine ◽  
Fpga Implementation ◽  
Greedy Heuristic ◽  
Logarithmic Barrier Function ◽  
Finite State ◽  
Field Programmable ◽  
Significant Area ◽  
Logarithmic Barrier

Recently, the Reconfigurable FSM has drawn the attention of the researchers for multistage signal processing applications. The optimal synthesis of Reconfigurable finite state machine with input multiplexing (Reconfigurable FSMIM) architecture is done by the iterative greedy heuristic based Hungarian algorithm (IGHA). The major problem concerning IGHA is the disintegration of a state encoding technique. This paper proposes the integration of IGHA with the state assignment using logarithmic barrier function based gradient descent approach to reduce the hardware consumption of Reconfigurable FSMIM. Experiments have been performed using MCNC FSM benchmarks which illustrate a significant area and speed improvement over other architectures during field programmable gate array (FPGA) implementation.

Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

2016 ◽  
Vol 10 (3) ◽  
pp. 163-172 ◽  
Author(s):  
Zarrin Tasnim Sworna ◽  
Mubin UlHaque ◽  
Nazma Tara ◽  
Hafiz Md. Hasan Babu ◽  
Ashis Kumar Biswas
Keyword(s):  
Low Power ◽  
Field Programmable Gate Array ◽  
Look Up Table ◽  
Field Programmable ◽  
Decimal Adder ◽  
Gate Array ◽  
Area Efficient

scholarly journals A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

2020 ◽  
Vol 9 (12) ◽  
pp. 217-220
Keyword(s):  
Field Programmable Gate Array ◽  
Test Pattern ◽  
Fault Coverage ◽  
Area Overhead ◽  
Field Programmable ◽  
Self Test ◽  
Gate Array ◽  
Built In Self Test ◽  
Pattern Generators ◽  
Logic Blocks

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

HARDWARE REDUCTION IN FPGA-BASED MOORE FSM

2013 ◽  
Vol 22 (03) ◽  
pp. 1350006 ◽  
Author(s):  
ALEXANDER BARKALOV ◽  
LARYSA TITARENKO ◽  
RAISA MALCHEVA ◽  
KYRYLL SOLDATOV
Keyword(s):  
Finite State Machine ◽  
State Machine ◽  
Logic Circuit ◽  
Embedded Memory ◽  
Look Up Table ◽  
Binary Encoding ◽  
Finite State

The methods are proposed targeting to reduce the numbers of both look-up table elements and embedded memory blocks in the logic circuit of a Moore finite state machine. The proposed methods are based on binary encoding of both classes of pseudoequivalent states and collections of microoperations. Examples of synthesis and results of investigations are given.

Efficient Utilization of FPGA Using LUT-6 Architecture

2012 ◽  
Vol 241-244 ◽  
pp. 2548-2554
Author(s):  
Razia Zia ◽  
Muzaffar Rao ◽  
Arshad Aziz ◽  
Pervez Akhtar
Keyword(s):  
Embedded Systems ◽  
Market Share ◽  
Boolean Functions ◽  
Field Programmable Gate Array ◽  
Efficient Utilization ◽  
Look Up Table ◽  
Fpga Architecture ◽  
Logic Block ◽  
Field Programmable ◽  
Typical Cell

Field Programmable gate array (FPGA) technology is continuously gaining market share and becoming essential part of the today’s modern embedded systems. The most common FPGA architecture consists of an array of logic blocks called Configurable Logic Block (CLB), I/O pads, and routing channels. In general, a logic block (CLB) consists of logical cells called Slices and other dedicated resources. A typical cell consists of LUTs (Look up table). In modern FPGAs, there are 6-input LUTs instead of 4-input LUTs. In this paper we present the use of 6-input LUT architecture for some Boolean functions (Mux8, Mux16, Mux32, Mux64, SOP64, OR40 and AND40).we show our results in terms of LUTs and Slices and these results are much better as compare to previously reported results that based on 4-input LUTs.

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