Impact of boron penetration at P/sup +/-poly/gate oxide interface on deep-submicron device reliability for dual-gate CMOS technologies

1997 ◽  
Vol 18 (5) ◽  
pp. 215-217 ◽  
Author(s):  
Ming-Yin Hao ◽  
D. Nayak ◽  
R. Rakkit
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
Oxide Interface ◽  
Device Reliability ◽  
Dual Gate ◽  
Boron Penetration

The Electrical Phenomena of Non-planar Structure and Devices using Plasma Doping

2005 ◽  
Vol 864 ◽  
Author(s):  
Jong-Heon Yang ◽  
In-Bok Baek ◽  
Kiju Im ◽  
Chang-Geun Ahn ◽  
Sungkweon Baek ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Thermal Annealing ◽  
Gate Oxide ◽  
Subthreshold Slope ◽  
Oxide Interface ◽  
Substrate Heating ◽  
Plasma Doping ◽  
Device Reliability ◽  
Research Show

AbstractWe fabricated narrow fins structures and non-planar MOSFETs like FinFETs and triple-gate MOSFETs using plasma doping with substrate heating under 350··, and measured their I-V characteristics. Fins and MOSFETs using low-temperature doping process show good current drivability and low subthreshold slope. However, without post high-temperature thermal annealing, this process could not avoid generating defects and traps as well as mobile protons on the gate and gate oxide interface and junctions, and therefore degraded device reliability. The results of ultra-small MOSFET research show possibility of new memory devices with these traps and ions in devices.

Impact of boron penetration on gate oxide reliability and device performance in a dual-gate oxide process

2000 ◽  
Author(s):  
Yunqiang Zhang ◽  
Chock H. Gan ◽  
Xi Li ◽  
James Lee ◽  
David Vigar ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Device Performance ◽  
Oxide Reliability ◽  
Dual Gate ◽  
Boron Penetration

Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide

1996 ◽  
Vol 35 (Part 1, No. 2B) ◽  
pp. 1496-1502 ◽  
Author(s):  
Kunihiro Suzuki ◽  
Akira Satoh ◽  
Takayuki Aoyama ◽  
Itaru Namura ◽  
Fumihiko Inoue ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
Thermal Budget ◽  
Dual Gate ◽  
Submicron Cmos

Thermal Budget for Fabricating A Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide

1995 ◽  
Author(s):  
Kunihiro Suzuki ◽  
Akira Satoh ◽  
Takayuki Aoyama ◽  
Itaru Namura ◽  
Fumihiko Inoue ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
Thermal Budget ◽  
Dual Gate ◽  
Submicron Cmos

Deep Submicron CMOS Technology Using Top-Edge Round STI and Dual Gate Oxide for Low Power 256 M-Bit Mobile DRAM

2003 ◽  
Vol 42 (Part 1, No. 4B) ◽  
pp. 1892-1896 ◽  
Author(s):  
Chihoon Lee ◽  
Donggun Park ◽  
Namhyuk Jo ◽  
Chanseong Hwang ◽  
Hyeong Joon Kim ◽  
...  
Keyword(s):  
Low Power ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Dual Gate ◽  
Submicron Cmos

Effect of N+ Ion Implantation and Gox Process on in and B Channel Profile

2000 ◽  
Vol 610 ◽  
Author(s):  
G. Curello ◽  
R. Rengarajan ◽  
J. Faul ◽  
H. Wurzer ◽  
J. Amon ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Deep Submicron ◽  
Short Channel ◽  
Gate Oxide Thickness ◽  
Process Effects ◽  
Dual Gate ◽  
N Dose ◽  
The Impact

AbstractIn this work, we report on the effect of different dual gate oxide (DGox) processes on the electrical properties of CMOS devices in deep submicron embedded DRAM (eDRAM) technology. Also discussed, is the effect of N+ Ion Implantation on the diffusion / segregation behaviour of B and In channel dopants. In particular, it will be shown that the N+ dose required to obtain a certain combination of dual gate oxide thickness varies with the gate oxide process. Effects of N+ dose on the In and B channel profiles are studied using SIMS. The impact of “thickness-equivalent” DGox processes on short channel effect (SCE) and carrier mobility is analyzed and tradeoffs for optimization of device performances are discussed.

RTA Processing of W-Polycide Dual-Gate Sub-Micron Structures for Low-Voltage CMOS Technology

1996 ◽  
Vol 429 ◽  
Author(s):  
J. Bevk ◽  
M. Furtsch ◽  
G. E. Georgiou ◽  
S. J. Hillenius ◽  
D. Schielein ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Low Voltage ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Atomic Diffusion ◽  
Cross Diffusion ◽  
Critical Issues ◽  
Simple Processing ◽  
Dual Gate ◽  
Boron Penetration

AbstractDeep submicron CMOS technology for low-power, low-voltage applications requires the use of symmetric n+/p+ poly gate structures. This requirement introduces a number of processing challenges, involving fundamental issues of atomic diffusion over distances of 1Å to ∼30μm. Two of the critical issues are dopant cross-diffusion between P- and NMOS devices with connected gates, resulting in large threshold voltage shifts, and boron penetration through the gate oxide. We show that in devices with W-polycide dual-gat:e structure most of these problems can be alleviated by using rapid thermal annealing, RTA, in combination with a few additional, simple processing steps (e. g., low-temperature recrystallization of a-Si layer and selective nitrogen coimplants). The RTA step, in particular, ensures thai: the boron activation in the p+ poly-Si remains high and negates any effects of arsenic cross-diffusion. CMOS devices with properly processed gates have low gate stack profiles, small threshold voltage shifts (<30mV), and excellent device characteristics.

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